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@@ -403,12 +403,27 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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int ret = 0;
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u32 pin_reg;
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unsigned long flags;
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+ u32 level_trig;
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+ u32 active_level;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
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spin_lock_irqsave(&gpio_dev->lock, flags);
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pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
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+ /*
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+ * When level_trig is set EDGE and active_level is set HIGH in BIOS
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+ * default settings, ignore incoming settings from client and use
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+ * BIOS settings to configure GPIO register.
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+ */
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+ level_trig = pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF);
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+ active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
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+
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+ if((!level_trig) &&
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+ ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) {
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+ type = IRQ_TYPE_EDGE_FALLING;
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+ }
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+
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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pin_reg &= ~BIT(LEVEL_TRIG_OFF);
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