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@@ -3364,6 +3364,30 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
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return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
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}
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+static void
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+skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
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+ uint16_t *minimum, uint16_t *y_minimum)
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+{
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+ const struct drm_plane_state *pstate;
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+ struct drm_plane *plane;
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+
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+ drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
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+ struct intel_plane *intel_plane = to_intel_plane(plane);
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+ int id = skl_wm_plane_id(intel_plane);
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+
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+ if (id == PLANE_CURSOR)
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+ continue;
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+
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+ if (!pstate->visible)
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+ continue;
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+
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+ minimum[id] = skl_ddb_min_alloc(pstate, 0);
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+ y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
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+ }
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+
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+ minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
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+}
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+
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static int
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skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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struct skl_ddb_allocation *ddb /* out */)
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@@ -3372,12 +3396,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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struct drm_crtc *crtc = cstate->base.crtc;
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struct drm_device *dev = crtc->dev;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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- struct intel_plane *intel_plane;
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- struct drm_plane *plane;
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- const struct drm_plane_state *pstate;
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enum pipe pipe = intel_crtc->pipe;
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struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
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- uint16_t alloc_size, start, cursor_blocks;
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+ uint16_t alloc_size, start;
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uint16_t minimum[I915_MAX_PLANES] = {};
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uint16_t y_minimum[I915_MAX_PLANES] = {};
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unsigned int total_data_rate;
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@@ -3405,32 +3426,22 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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return 0;
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}
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- cursor_blocks = skl_cursor_allocation(num_active);
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- ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
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- ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
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-
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- alloc_size -= cursor_blocks;
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-
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- /* 1. Allocate the mininum required blocks for each active plane */
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- drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
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- intel_plane = to_intel_plane(plane);
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- id = skl_wm_plane_id(intel_plane);
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-
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- if (!pstate->visible)
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- continue;
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-
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- if (plane->type == DRM_PLANE_TYPE_CURSOR)
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- continue;
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+ skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
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- minimum[id] = skl_ddb_min_alloc(pstate, 0);
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- y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
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- }
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+ /*
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+ * 1. Allocate the mininum required blocks for each active plane
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+ * and allocate the cursor, it doesn't require extra allocation
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+ * proportional to the data rate.
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+ */
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- for (i = 0; i < PLANE_CURSOR; i++) {
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+ for (i = 0; i < I915_MAX_PLANES; i++) {
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alloc_size -= minimum[i];
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alloc_size -= y_minimum[i];
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}
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+ ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
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+ ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
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+
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/*
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* 2. Distribute the remaining space in proportion to the amount of
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* data each plane needs to fetch from memory.
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@@ -3448,6 +3459,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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unsigned int data_rate, y_data_rate;
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uint16_t plane_blocks, y_plane_blocks = 0;
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+ if (id == PLANE_CURSOR)
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+ continue;
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+
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data_rate = plane_data_rate[id];
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/*
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