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@@ -27,6 +27,7 @@
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#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
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#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
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#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
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+#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
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#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
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#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
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@@ -34,6 +35,7 @@
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#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
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#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
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#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
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+#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
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#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
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#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
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