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@@ -233,7 +233,7 @@ enum amdgpu_kiq_irq {
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#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
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#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
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-#define MAX_KIQ_REG_TRY 20
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+#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
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int amdgpu_device_ip_set_clockgating_state(void *dev,
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enum amd_ip_block_type block_type,
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