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@@ -817,6 +817,25 @@ static bool is_shadowed_mmio(unsigned int offset)
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return ret;
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}
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+static inline bool is_force_nonpriv_mmio(unsigned int offset)
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+{
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+ return (offset >= 0x24d0 && offset < 0x2500);
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+}
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+
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+static int force_nonpriv_reg_handler(struct parser_exec_state *s,
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+ unsigned int offset, unsigned int index)
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+{
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+ struct intel_gvt *gvt = s->vgpu->gvt;
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+ unsigned int data = cmd_val(s, index + 1);
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+
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+ if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {
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+ gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
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+ offset, data);
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+ return -EINVAL;
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+ }
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+ return 0;
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+}
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+
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static int cmd_reg_handler(struct parser_exec_state *s,
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unsigned int offset, unsigned int index, char *cmd)
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{
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@@ -841,6 +860,10 @@ static int cmd_reg_handler(struct parser_exec_state *s,
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return 0;
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}
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+ if (is_force_nonpriv_mmio(offset) &&
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+ force_nonpriv_reg_handler(s, offset, index))
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+ return -EINVAL;
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+
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if (offset == i915_mmio_reg_offset(DERRMR) ||
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offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
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/* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
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