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@@ -1504,73 +1504,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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1: addi r8,r8,16
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.endr
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- /* Save DEC */
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- mfspr r5,SPRN_DEC
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- mftb r6
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- extsw r5,r5
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- add r5,r5,r6
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- std r5,VCPU_DEC_EXPIRES(r9)
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-
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-BEGIN_FTR_SECTION
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- b 8f
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-END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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- /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
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- mfmsr r8
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- li r0, 1
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- rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
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- mtmsrd r8
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-
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- /* Save POWER8-specific registers */
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- mfspr r5, SPRN_IAMR
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- mfspr r6, SPRN_PSPB
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- mfspr r7, SPRN_FSCR
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- std r5, VCPU_IAMR(r9)
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- stw r6, VCPU_PSPB(r9)
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- std r7, VCPU_FSCR(r9)
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- mfspr r5, SPRN_IC
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- mfspr r6, SPRN_VTB
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- mfspr r7, SPRN_TAR
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- std r5, VCPU_IC(r9)
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- std r6, VCPU_VTB(r9)
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- std r7, VCPU_TAR(r9)
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-#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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- mfspr r5, SPRN_TFHAR
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- mfspr r6, SPRN_TFIAR
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- mfspr r7, SPRN_TEXASR
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- std r5, VCPU_TFHAR(r9)
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- std r6, VCPU_TFIAR(r9)
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- std r7, VCPU_TEXASR(r9)
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-#endif
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- mfspr r8, SPRN_EBBHR
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- std r8, VCPU_EBBHR(r9)
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- mfspr r5, SPRN_EBBRR
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- mfspr r6, SPRN_BESCR
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- mfspr r7, SPRN_CSIGR
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- mfspr r8, SPRN_TACR
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- std r5, VCPU_EBBRR(r9)
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- std r6, VCPU_BESCR(r9)
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- std r7, VCPU_CSIGR(r9)
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- std r8, VCPU_TACR(r9)
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- mfspr r5, SPRN_TCSCR
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- mfspr r6, SPRN_ACOP
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- mfspr r7, SPRN_PID
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- mfspr r8, SPRN_WORT
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- std r5, VCPU_TCSCR(r9)
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- std r6, VCPU_ACOP(r9)
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- stw r7, VCPU_GUEST_PID(r9)
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- std r8, VCPU_WORT(r9)
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-8:
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-
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- /* Save and reset AMR and UAMOR before turning on the MMU */
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-BEGIN_FTR_SECTION
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- mfspr r5,SPRN_AMR
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- mfspr r6,SPRN_UAMOR
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- std r5,VCPU_AMR(r9)
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- std r6,VCPU_UAMOR(r9)
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- li r6,0
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- mtspr SPRN_AMR,r6
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-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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-
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/* Unset guest mode */
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li r0, KVM_GUEST_MODE_NONE
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stb r0, HSTATE_IN_GUEST(r13)
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@@ -2203,7 +2136,7 @@ BEGIN_FTR_SECTION
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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#endif
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mfspr r6,SPRN_VRSAVE
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- stw r6,VCPU_VRSAVE(r3)
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+ stw r6,VCPU_VRSAVE(r31)
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mtlr r30
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mtmsrd r5
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isync
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@@ -2240,7 +2173,7 @@ BEGIN_FTR_SECTION
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bl .load_vr_state
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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#endif
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- lwz r7,VCPU_VRSAVE(r4)
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+ lwz r7,VCPU_VRSAVE(r31)
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mtspr SPRN_VRSAVE,r7
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mtlr r30
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mr r4,r31
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