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@@ -1110,7 +1110,6 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
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static int i915_frequency_info(struct seq_file *m, void *unused)
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{
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struct drm_i915_private *dev_priv = node_to_i915(m->private);
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- struct drm_device *dev = &dev_priv->drm;
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int ret = 0;
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intel_runtime_pm_get(dev_priv);
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@@ -1173,10 +1172,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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}
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/* RPSTAT1 is in the GT power well */
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- ret = mutex_lock_interruptible(&dev->struct_mutex);
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- if (ret)
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- goto out;
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-
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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reqf = I915_READ(GEN6_RPNSWREQ);
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@@ -1211,7 +1206,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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cagf = intel_gpu_freq(dev_priv, cagf);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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- mutex_unlock(&dev->struct_mutex);
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if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
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pm_ier = I915_READ(GEN6_PMIER);
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@@ -1301,7 +1295,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
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seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
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-out:
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intel_runtime_pm_put(dev_priv);
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return ret;
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}
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