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+/*
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+ * Copyright (C) ST-Ericsson SA 2011
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+ *
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+ * License Terms: GNU General Public License v2
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+ * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
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+ * Author: Sundar Iyer for ST-Ericsson
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+ * sched_clock implementation is based on:
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+ * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
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+ *
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+ * DBx500-PRCMU Timer
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+ * The PRCMU has 5 timers which are available in a always-on
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+ * power domain. We use the Timer 4 for our always-on clock
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+ * source on DB8500 and Timer 3 on DB5500.
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+ */
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+#include <linux/clockchips.h>
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+#include <linux/clksrc-dbx500-prcmu.h>
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+
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+#include <asm/sched_clock.h>
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+
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+#include <mach/setup.h>
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+#include <mach/hardware.h>
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+
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+#define RATE_32K 32768
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+
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+#define TIMER_MODE_CONTINOUS 0x1
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+#define TIMER_DOWNCOUNT_VAL 0xffffffff
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+
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+#define PRCMU_TIMER_REF 0
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+#define PRCMU_TIMER_DOWNCOUNT 0x4
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+#define PRCMU_TIMER_MODE 0x8
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+
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+#define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */
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+
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+void __iomem *clksrc_dbx500_timer_base;
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+
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+static cycle_t clksrc_dbx500_prcmu_read(struct clocksource *cs)
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+{
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+ u32 count, count2;
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+
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+ do {
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+ count = readl(clksrc_dbx500_timer_base +
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+ PRCMU_TIMER_DOWNCOUNT);
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+ count2 = readl(clksrc_dbx500_timer_base +
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+ PRCMU_TIMER_DOWNCOUNT);
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+ } while (count2 != count);
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+
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+ /* Negate because the timer is a decrementing counter */
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+ return ~count;
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+}
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+
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+static struct clocksource clocksource_dbx500_prcmu = {
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+ .name = "dbx500-prcmu-timer",
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+ .rating = 300,
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+ .read = clksrc_dbx500_prcmu_read,
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+ .shift = 10,
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+ .mask = CLOCKSOURCE_MASK(32),
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+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
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+};
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+
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+#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
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+static DEFINE_CLOCK_DATA(cd);
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+
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+unsigned long long notrace sched_clock(void)
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+{
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+ u32 cyc;
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+
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+ if (unlikely(!clksrc_dbx500_timer_base))
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+ return 0;
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+
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+ cyc = clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
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+
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+ return cyc_to_sched_clock(&cd, cyc, (u32)~0);
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+}
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+
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+static void notrace clksrc_dbx500_prcmu_update_sched_clock(void)
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+{
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+ u32 cyc = clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
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+ update_sched_clock(&cd, cyc, (u32)~0);
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+}
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+#endif
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+
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+void __init clksrc_dbx500_prcmu_init(void)
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+{
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+ /*
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+ * The A9 sub system expects the timer to be configured as
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+ * a continous looping timer.
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+ * The PRCMU should configure it but if it for some reason
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+ * don't we do it here.
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+ */
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+ if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
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+ TIMER_MODE_CONTINOUS) {
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+ writel(TIMER_MODE_CONTINOUS,
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+ clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
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+ writel(TIMER_DOWNCOUNT_VAL,
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+ clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
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+ }
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+#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
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+ init_sched_clock(&cd, clksrc_dbx500_prcmu_update_sched_clock,
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+ 32, RATE_32K);
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+#endif
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+ clocksource_calc_mult_shift(&clocksource_dbx500_prcmu,
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+ RATE_32K, SCHED_CLOCK_MIN_WRAP);
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+ clocksource_register(&clocksource_dbx500_prcmu);
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+}
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