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@@ -39,16 +39,6 @@ static inline void destroy_context(struct mm_struct *mm)
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{
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{
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}
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}
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-static inline void set_pgdir(pgd_t *pgd)
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-{
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- /*
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- * Use the old spbtr name instead of using the current satp
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- * name to support binutils 2.29 which doesn't know about the
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- * privileged ISA 1.10 yet.
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- */
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- csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE);
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-}
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-
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/*
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/*
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* When necessary, performs a deferred icache flush for the given MM context,
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* When necessary, performs a deferred icache flush for the given MM context,
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* on the local CPU. RISC-V has no direct mechanism for instruction cache
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* on the local CPU. RISC-V has no direct mechanism for instruction cache
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@@ -93,7 +83,12 @@ static inline void switch_mm(struct mm_struct *prev,
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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- set_pgdir(next->pgd);
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+ /*
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+ * Use the old spbtr name instead of using the current satp
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+ * name to support binutils 2.29 which doesn't know about the
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+ * privileged ISA 1.10 yet.
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+ */
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+ csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE);
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local_flush_tlb_all();
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local_flush_tlb_all();
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flush_icache_deferred(next);
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flush_icache_deferred(next);
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