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@@ -173,13 +173,7 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
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channel->status = MUSB_DMA_STATUS_FREE;
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- /* Handle only RX callbacks here. TX callbacks must be handled based
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- * on the TUSB DMA status interrupt.
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- * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback
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- * interrupt for RX and TX.
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- */
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- if (!chdat->tx)
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- musb_dma_completion(musb, chdat->epnum, chdat->tx);
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+ musb_dma_completion(musb, chdat->epnum, chdat->tx);
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/* We must terminate short tx transfers manually by setting TXPKTRDY.
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* REVISIT: This same problem may occur with other MUSB dma as well.
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@@ -464,22 +458,12 @@ tusb_omap_dma_allocate(struct dma_controller *c,
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int ret, i;
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struct tusb_omap_dma *tusb_dma;
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struct musb *musb;
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- void __iomem *tbase;
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struct dma_channel *channel = NULL;
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struct tusb_omap_dma_ch *chdat = NULL;
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struct tusb_dma_data *dma_data = NULL;
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- u32 reg;
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tusb_dma = container_of(c, struct tusb_omap_dma, controller);
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musb = tusb_dma->controller.musb;
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- tbase = musb->ctrl_base;
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-
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- reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
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- if (tx)
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- reg &= ~(1 << hw_ep->epnum);
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- else
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- reg &= ~(1 << (hw_ep->epnum + 15));
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- musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
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/* REVISIT: Why does dmareq5 not work? */
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if (hw_ep->epnum == 0) {
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@@ -548,26 +532,10 @@ static void tusb_omap_dma_release(struct dma_channel *channel)
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{
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struct tusb_omap_dma_ch *chdat = to_chdat(channel);
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struct musb *musb = chdat->musb;
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- void __iomem *tbase = musb->ctrl_base;
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- u32 reg;
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dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum,
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chdat->dma_data->ch);
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- reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
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- if (chdat->tx)
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- reg |= (1 << chdat->epnum);
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- else
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- reg |= (1 << (chdat->epnum + 15));
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- musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
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-
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- reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR);
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- if (chdat->tx)
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- reg |= (1 << chdat->epnum);
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- else
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- reg |= (1 << (chdat->epnum + 15));
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- musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg);
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-
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channel->status = MUSB_DMA_STATUS_UNKNOWN;
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omap_stop_dma(chdat->dma_data->ch);
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