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@@ -2027,7 +2027,7 @@ enum i915_power_well_id {
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#define _CNL_PORT_TX_DW5_LN0_AE 0x162454
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#define _CNL_PORT_TX_DW5_LN0_B 0x162654
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#define _CNL_PORT_TX_DW5_LN0_C 0x162C54
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-#define _CNL_PORT_TX_DW5_LN0_D 0x162ED4
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+#define _CNL_PORT_TX_DW5_LN0_D 0x162E54
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#define _CNL_PORT_TX_DW5_LN0_F 0x162854
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#define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW5_GRP_AE, \
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@@ -2058,7 +2058,7 @@ enum i915_power_well_id {
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#define _CNL_PORT_TX_DW7_LN0_AE 0x16245C
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#define _CNL_PORT_TX_DW7_LN0_B 0x16265C
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#define _CNL_PORT_TX_DW7_LN0_C 0x162C5C
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-#define _CNL_PORT_TX_DW7_LN0_D 0x162EDC
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+#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C
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#define _CNL_PORT_TX_DW7_LN0_F 0x16285C
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#define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \
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_CNL_PORT_TX_DW7_GRP_AE, \
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