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@@ -19,18 +19,30 @@
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/interrupt.h>
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-#include <linux/reboot.h>
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#include <linux/bitops.h>
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-#define GIO_BANK_SIZE 0x20
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-#define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00)
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-#define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04)
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-#define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08)
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-#define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c)
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-#define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10)
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-#define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14)
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-#define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18)
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-#define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c)
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+enum gio_reg_index {
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+ GIO_REG_ODEN = 0,
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+ GIO_REG_DATA,
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+ GIO_REG_IODIR,
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+ GIO_REG_EC,
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+ GIO_REG_EI,
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+ GIO_REG_MASK,
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+ GIO_REG_LEVEL,
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+ GIO_REG_STAT,
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+ NUMBER_OF_GIO_REGISTERS
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+};
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+
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+#define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
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+#define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
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+#define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
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+#define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
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+#define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
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+#define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
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+#define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
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+#define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
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+#define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
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+#define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
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struct brcmstb_gpio_bank {
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struct list_head node;
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@@ -38,6 +50,8 @@ struct brcmstb_gpio_bank {
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struct gpio_chip gc;
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struct brcmstb_gpio_priv *parent_priv;
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u32 width;
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+ u32 wake_active;
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+ u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
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};
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struct brcmstb_gpio_priv {
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@@ -50,7 +64,6 @@ struct brcmstb_gpio_priv {
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int gpio_base;
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int num_gpios;
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int parent_wake_irq;
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- struct notifier_block reboot_notifier;
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};
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#define MAX_GPIO_PER_BANK 32
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@@ -66,15 +79,22 @@ brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
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}
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static unsigned long
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-brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
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+__brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
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{
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void __iomem *reg_base = bank->parent_priv->reg_base;
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+
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+ return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
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+ bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
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+}
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+
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+static unsigned long
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+brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
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+{
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unsigned long status;
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unsigned long flags;
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spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
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- status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
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- bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
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+ status = __brcmstb_gpio_get_active_irqs(bank);
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spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
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return status;
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@@ -210,11 +230,6 @@ static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
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{
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int ret = 0;
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- /*
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- * Only enable wake IRQ once for however many hwirqs can wake
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- * since they all use the same wake IRQ. Mask will be set
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- * up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
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- */
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if (enable)
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ret = enable_irq_wake(priv->parent_wake_irq);
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else
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@@ -228,7 +243,18 @@ static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
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static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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- struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
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+ struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
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+ struct brcmstb_gpio_priv *priv = bank->parent_priv;
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+ u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
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+
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+ /*
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+ * Do not do anything specific for now, suspend/resume callbacks will
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+ * configure the interrupt mask appropriately
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+ */
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+ if (enable)
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+ bank->wake_active |= mask;
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+ else
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+ bank->wake_active &= ~mask;
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return brcmstb_gpio_priv_set_wake(priv, enable);
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}
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@@ -239,7 +265,8 @@ static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
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if (!priv || irq != priv->parent_wake_irq)
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return IRQ_NONE;
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- pm_wakeup_event(&priv->pdev->dev, 0);
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+
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+ /* Nothing to do */
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return IRQ_HANDLED;
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}
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@@ -280,19 +307,6 @@ static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
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chained_irq_exit(chip, desc);
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}
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-static int brcmstb_gpio_reboot(struct notifier_block *nb,
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- unsigned long action, void *data)
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-{
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- struct brcmstb_gpio_priv *priv =
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- container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
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-
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- /* Enable GPIO for S5 cold boot */
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- if (action == SYS_POWER_OFF)
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- brcmstb_gpio_priv_set_wake(priv, 1);
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-
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- return NOTIFY_DONE;
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-}
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-
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static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
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struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
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{
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@@ -397,12 +411,6 @@ static int brcmstb_gpio_remove(struct platform_device *pdev)
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list_for_each_entry(bank, &priv->bank_list, node)
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gpiochip_remove(&bank->gc);
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- if (priv->reboot_notifier.notifier_call) {
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- ret = unregister_reboot_notifier(&priv->reboot_notifier);
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- if (ret)
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- dev_err(&pdev->dev,
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- "failed to unregister reboot notifier\n");
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- }
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return ret;
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}
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@@ -462,9 +470,8 @@ static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
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"Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
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} else {
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/*
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- * Set wakeup capability before requesting wakeup
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- * interrupt, so we can process boot-time "wakeups"
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- * (e.g., from S5 cold boot)
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+ * Set wakeup capability so we can process boot-time
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+ * "wakeups" (e.g., from S5 cold boot)
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*/
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device_set_wakeup_capable(dev, true);
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device_wakeup_enable(dev);
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@@ -477,10 +484,6 @@ static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
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dev_err(dev, "Couldn't request wake IRQ");
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goto out_free_domain;
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}
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-
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- priv->reboot_notifier.notifier_call =
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- brcmstb_gpio_reboot;
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- register_reboot_notifier(&priv->reboot_notifier);
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}
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}
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@@ -491,14 +494,12 @@ static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
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priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
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priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
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- /* Ensures that all non-wakeup IRQs are disabled at suspend */
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- priv->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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-
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if (priv->parent_wake_irq)
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priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
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irq_set_chained_handler_and_data(priv->parent_irq,
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brcmstb_gpio_irq_handler, priv);
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+ irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
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return 0;
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@@ -508,6 +509,99 @@ out_free_domain:
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return err;
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}
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+static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
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+ struct brcmstb_gpio_bank *bank)
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+{
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+ struct gpio_chip *gc = &bank->gc;
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+ unsigned int i;
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+
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+ for (i = 0; i < GIO_REG_STAT; i++)
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+ bank->saved_regs[i] = gc->read_reg(priv->reg_base +
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+ GIO_BANK_OFF(bank->id, i));
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+}
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+
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+static void brcmstb_gpio_quiesce(struct device *dev, bool save)
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+{
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+ struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
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+ struct brcmstb_gpio_bank *bank;
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+ struct gpio_chip *gc;
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+ u32 imask;
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+
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+ /* disable non-wake interrupt */
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+ if (priv->parent_irq >= 0)
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+ disable_irq(priv->parent_irq);
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+
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+ list_for_each_entry(bank, &priv->bank_list, node) {
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+ gc = &bank->gc;
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+
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+ if (save)
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+ brcmstb_gpio_bank_save(priv, bank);
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+
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+ /* Unmask GPIOs which have been flagged as wake-up sources */
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+ if (priv->parent_wake_irq)
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+ imask = bank->wake_active;
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+ else
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+ imask = 0;
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+ gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
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+ imask);
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+ }
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+}
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+
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+static void brcmstb_gpio_shutdown(struct platform_device *pdev)
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+{
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+ /* Enable GPIO for S5 cold boot */
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+ brcmstb_gpio_quiesce(&pdev->dev, false);
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+}
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+
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+#ifdef CONFIG_PM_SLEEP
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+static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
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+ struct brcmstb_gpio_bank *bank)
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+{
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+ struct gpio_chip *gc = &bank->gc;
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+ unsigned int i;
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+
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+ for (i = 0; i < GIO_REG_STAT; i++)
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+ gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
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+ bank->saved_regs[i]);
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+}
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+
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+static int brcmstb_gpio_suspend(struct device *dev)
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+{
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+ brcmstb_gpio_quiesce(dev, true);
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+ return 0;
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+}
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+
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+static int brcmstb_gpio_resume(struct device *dev)
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+{
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+ struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
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+ struct brcmstb_gpio_bank *bank;
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+ bool need_wakeup_event = false;
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+
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+ list_for_each_entry(bank, &priv->bank_list, node) {
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+ need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
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+ brcmstb_gpio_bank_restore(priv, bank);
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+ }
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+
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+ if (priv->parent_wake_irq && need_wakeup_event)
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+ pm_wakeup_event(dev, 0);
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+
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+ /* enable non-wake interrupt */
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+ if (priv->parent_irq >= 0)
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+ enable_irq(priv->parent_irq);
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+
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+ return 0;
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+}
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+
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+#else
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+#define brcmstb_gpio_suspend NULL
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+#define brcmstb_gpio_resume NULL
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+#endif /* CONFIG_PM_SLEEP */
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+
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+static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
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+ .suspend_noirq = brcmstb_gpio_suspend,
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+ .resume_noirq = brcmstb_gpio_resume,
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+};
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+
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static int brcmstb_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@@ -522,6 +616,7 @@ static int brcmstb_gpio_probe(struct platform_device *pdev)
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int err;
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static int gpio_base;
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unsigned long flags = 0;
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+ bool need_wakeup_event = false;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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@@ -617,6 +712,7 @@ static int brcmstb_gpio_probe(struct platform_device *pdev)
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* Mask all interrupts by default, since wakeup interrupts may
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* be retained from S5 cold boot
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*/
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+ need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
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gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
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err = gpiochip_add_data(gc, bank);
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@@ -646,6 +742,9 @@ static int brcmstb_gpio_probe(struct platform_device *pdev)
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dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
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num_banks, priv->gpio_base, gpio_base - 1);
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+ if (priv->parent_wake_irq && need_wakeup_event)
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+ pm_wakeup_event(dev, 0);
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+
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return 0;
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fail:
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@@ -664,9 +763,11 @@ static struct platform_driver brcmstb_gpio_driver = {
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.driver = {
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.name = "brcmstb-gpio",
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.of_match_table = brcmstb_gpio_of_match,
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+ .pm = &brcmstb_gpio_pm_ops,
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},
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.probe = brcmstb_gpio_probe,
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.remove = brcmstb_gpio_remove,
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+ .shutdown = brcmstb_gpio_shutdown,
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};
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module_platform_driver(brcmstb_gpio_driver);
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