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@@ -173,13 +173,17 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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{
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struct sun4i_spi *sspi = spi_master_get_devdata(master);
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unsigned int mclk_rate, div, timeout;
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+ unsigned int start, end, tx_time;
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unsigned int tx_len = 0;
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int ret = 0;
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u32 reg;
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/* We don't support transfer larger than the FIFO */
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if (tfr->len > SUN4I_FIFO_DEPTH)
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- return -EINVAL;
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+ return -EMSGSIZE;
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+
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+ if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH)
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+ return -EMSGSIZE;
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reinit_completion(&sspi->done);
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sspi->tx_buf = tfr->tx_buf;
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@@ -269,8 +273,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
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sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
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- /* Fill the TX FIFO */
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- sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
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+ /*
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+ * Fill the TX FIFO
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+ * Filling the FIFO fully causes timeout for some reason
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+ * at least on spi2 on A10s
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+ */
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+ sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
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/* Enable the interrupts */
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sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
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@@ -279,9 +287,16 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
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sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
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+ tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
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+ start = jiffies;
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timeout = wait_for_completion_timeout(&sspi->done,
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- msecs_to_jiffies(1000));
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+ msecs_to_jiffies(tx_time));
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+ end = jiffies;
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if (!timeout) {
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+ dev_warn(&master->dev,
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+ "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
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+ dev_name(&spi->dev), tfr->len, tfr->speed_hz,
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+ jiffies_to_msecs(end - start), tx_time);
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ret = -ETIMEDOUT;
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goto out;
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}
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