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@@ -60,6 +60,22 @@ Optional properties:
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be specified.
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- phy-clkgate-delay-us: the delay time (us) between putting the PHY into
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low power mode and gating the PHY clock.
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+- non-zero-ttctrl-ttha: after setting this property, the value of register
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+ ttctrl.ttha will be 0x7f; if not, the value will be 0x0, this is the default
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+ value. It needs to be very carefully for setting this property, it is
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+ recommended that consult with your IC engineer before setting this value.
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+ On the most of chipidea platforms, the "usage_tt" flag at RTL is 0, so this
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+ property only affects siTD.
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+ If this property is not set, the max packet size is 1023 bytes, and if
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+ the total of packet size for pervious transactions are more than 256 bytes,
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+ it can't accept any transactions within this frame. The use case is single
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+ transaction, but higher frame rate.
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+ If this property is set, the max packet size is 188 bytes, it can handle
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+ more transactions than above case, it can accept transactions until it
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+ considers the left room size within frame is less than 188 bytes, software
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+ needs to make sure it does not send more than 90%
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+ maximum_periodic_data_per_frame. The use case is multiple transactions, but
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+ less frame rate.
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i.mx specific properties
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- fsl,usbmisc: phandler of non-core register device, with one
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