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@@ -35,12 +35,10 @@
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#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
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#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
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-/* PEX LUT registers */
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-#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */
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-
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struct ls_pcie_drvdata {
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u32 lut_offset;
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u32 ltssm_shift;
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+ u32 lut_dbg;
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struct pcie_host_ops *ops;
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};
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@@ -134,7 +132,7 @@ static int ls_pcie_link_up(struct pcie_port *pp)
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struct ls_pcie *pcie = to_ls_pcie(pp);
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u32 state;
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- state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
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+ state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
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pcie->drvdata->ltssm_shift) &
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LTSSM_STATE_MASK;
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@@ -196,18 +194,28 @@ static struct ls_pcie_drvdata ls1021_drvdata = {
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static struct ls_pcie_drvdata ls1043_drvdata = {
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.lut_offset = 0x10000,
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.ltssm_shift = 24,
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+ .lut_dbg = 0x7fc,
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+ .ops = &ls_pcie_host_ops,
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+};
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+
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+static struct ls_pcie_drvdata ls1046_drvdata = {
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+ .lut_offset = 0x80000,
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+ .ltssm_shift = 24,
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+ .lut_dbg = 0x407fc,
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.ops = &ls_pcie_host_ops,
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};
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static struct ls_pcie_drvdata ls2080_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 0,
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+ .lut_dbg = 0x7fc,
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.ops = &ls_pcie_host_ops,
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};
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static const struct of_device_id ls_pcie_of_match[] = {
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{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
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{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
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+ { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
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{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
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{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
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{ },
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@@ -251,10 +259,8 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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pcie->pp.dbi_base = devm_ioremap_resource(dev, dbi_base);
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- if (IS_ERR(pcie->pp.dbi_base)) {
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- dev_err(dev, "missing *regs* space\n");
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+ if (IS_ERR(pcie->pp.dbi_base))
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return PTR_ERR(pcie->pp.dbi_base);
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- }
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pcie->drvdata = match->data;
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pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset;
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