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@@ -74,6 +74,43 @@ static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
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}
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}
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+static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
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+{
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+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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+ enum port port;
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+ u32 tmp;
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+ u32 lane_mask;
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+
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+ switch (intel_dsi->lane_count) {
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+ case 1:
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+ lane_mask = PWR_DOWN_LN_3_1_0;
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+ break;
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+ case 2:
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+ lane_mask = PWR_DOWN_LN_3_1;
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+ break;
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+ case 3:
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+ lane_mask = PWR_DOWN_LN_3;
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+ break;
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+ case 4:
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+ default:
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+ lane_mask = PWR_UP_ALL_LANES;
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+ break;
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+ }
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+
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+ for_each_dsi_port(port, intel_dsi->ports) {
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+ tmp = I915_READ(ICL_PORT_CL_DW10(port));
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+ tmp &= ~PWR_DOWN_LN_MASK;
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+ I915_WRITE(ICL_PORT_CL_DW10(port), tmp | lane_mask);
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+ }
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+}
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+
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+static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
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+{
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+ /* step 4a: power up all lanes of the DDI used by DSI */
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+ gen11_dsi_power_up_lanes(encoder);
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+}
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+
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static void __attribute__((unused))
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gen11_dsi_pre_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config,
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@@ -84,4 +121,7 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
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/* step3: enable DSI PLL */
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gen11_dsi_program_esc_clk_div(encoder);
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+
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+ /* step4: enable DSI port and DPHY */
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+ gen11_dsi_enable_port_and_phy(encoder);
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}
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