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@@ -7,8 +7,6 @@ Required properties:
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- reg: Physical base address and length of the registers of controller
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- reg: Physical base address and length of the registers of controller
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- reg-names: The names of register regions. The following regions are required:
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- reg-names: The names of register regions. The following regions are required:
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* "dsi_ctrl"
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* "dsi_ctrl"
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-- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
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- be 0 or 1, since we have 2 DSI controllers at most for now.
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- interrupts: The interrupt signal from the DSI block.
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- interrupts: The interrupt signal from the DSI block.
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- clocks: Phandles to device clocks.
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- clocks: Phandles to device clocks.
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@@ -96,8 +94,6 @@ Required properties:
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* "dsi_phy_regulator"
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* "dsi_phy_regulator"
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- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
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- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
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2 clocks: A byte clock (index 0), and a pixel clock (index 1).
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2 clocks: A byte clock (index 0), and a pixel clock (index 1).
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-- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
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- be 0 or 1, since we have 2 DSI PHYs at most for now.
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- clocks: Phandles to device clocks. See [1] for details on clock bindings.
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- clocks: Phandles to device clocks. See [1] for details on clock bindings.
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- clock-names: the following clocks are required:
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- clock-names: the following clocks are required:
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