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@@ -0,0 +1,686 @@
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+/*
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+ * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
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+ *
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+ * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
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+ * Jason ported to M54418TWR and MVFA5 (VF610).
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+ * Authors: Stefan Agner <stefan.agner@toradex.com>
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+ * Bill Pringlemeir <bpringlemeir@nbsps.com>
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+ * Shaohui Xie <b21989@freescale.com>
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+ * Jason Jin <Jason.jin@freescale.com>
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+ *
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+ * Based on original driver mpc5121_nfc.c.
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+ *
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+ * This is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * Limitations:
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+ * - Untested on MPC5125 and M54418.
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+ * - DMA and pipelining not used.
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+ * - 2K pages or less.
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+ * - No chip select, one NAND chip per controller.
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+ * - No hardware ECC.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/bitops.h>
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/init.h>
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/nand.h>
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+#include <linux/mtd/partitions.h>
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+#include <linux/of_mtd.h>
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+#include <linux/of_device.h>
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+#include <linux/platform_device.h>
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+#include <linux/slab.h>
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+
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+#define DRV_NAME "vf610_nfc"
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+
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+/* Register Offsets */
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+#define NFC_FLASH_CMD1 0x3F00
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+#define NFC_FLASH_CMD2 0x3F04
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+#define NFC_COL_ADDR 0x3F08
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+#define NFC_ROW_ADDR 0x3F0c
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+#define NFC_ROW_ADDR_INC 0x3F14
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+#define NFC_FLASH_STATUS1 0x3F18
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+#define NFC_FLASH_STATUS2 0x3F1c
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+#define NFC_CACHE_SWAP 0x3F28
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+#define NFC_SECTOR_SIZE 0x3F2c
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+#define NFC_FLASH_CONFIG 0x3F30
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+#define NFC_IRQ_STATUS 0x3F38
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+
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+/* Addresses for NFC MAIN RAM BUFFER areas */
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+#define NFC_MAIN_AREA(n) ((n) * 0x1000)
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+
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+#define PAGE_2K 0x0800
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+#define OOB_64 0x0040
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+#define OOB_MAX 0x0100
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+
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+/*
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+ * NFC_CMD2[CODE] values. See section:
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+ * - 31.4.7 Flash Command Code Description, Vybrid manual
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+ * - 23.8.6 Flash Command Sequencer, MPC5125 manual
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+ *
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+ * Briefly these are bitmasks of controller cycles.
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+ */
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+#define READ_PAGE_CMD_CODE 0x7EE0
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+#define READ_ONFI_PARAM_CMD_CODE 0x4860
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+#define PROGRAM_PAGE_CMD_CODE 0x7FC0
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+#define ERASE_CMD_CODE 0x4EC0
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+#define READ_ID_CMD_CODE 0x4804
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+#define RESET_CMD_CODE 0x4040
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+#define STATUS_READ_CMD_CODE 0x4068
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+
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+/* NFC ECC mode define */
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+#define ECC_BYPASS 0
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+
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+/*** Register Mask and bit definitions */
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+
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+/* NFC_FLASH_CMD1 Field */
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+#define CMD_BYTE2_MASK 0xFF000000
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+#define CMD_BYTE2_SHIFT 24
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+
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+/* NFC_FLASH_CM2 Field */
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+#define CMD_BYTE1_MASK 0xFF000000
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+#define CMD_BYTE1_SHIFT 24
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+#define CMD_CODE_MASK 0x00FFFF00
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+#define CMD_CODE_SHIFT 8
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+#define BUFNO_MASK 0x00000006
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+#define BUFNO_SHIFT 1
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+#define START_BIT BIT(0)
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+
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+/* NFC_COL_ADDR Field */
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+#define COL_ADDR_MASK 0x0000FFFF
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+#define COL_ADDR_SHIFT 0
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+
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+/* NFC_ROW_ADDR Field */
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+#define ROW_ADDR_MASK 0x00FFFFFF
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+#define ROW_ADDR_SHIFT 0
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+#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
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+#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
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+#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
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+#define ROW_ADDR_CHIP_SEL_SHIFT 24
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+
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+/* NFC_FLASH_STATUS2 Field */
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+#define STATUS_BYTE1_MASK 0x000000FF
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+
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+/* NFC_FLASH_CONFIG Field */
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+#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
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+#define CONFIG_ECC_SRAM_ADDR_SHIFT 22
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+#define CONFIG_ECC_SRAM_REQ_BIT BIT(21)
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+#define CONFIG_DMA_REQ_BIT BIT(20)
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+#define CONFIG_ECC_MODE_MASK 0x000E0000
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+#define CONFIG_ECC_MODE_SHIFT 17
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+#define CONFIG_FAST_FLASH_BIT BIT(16)
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+#define CONFIG_16BIT BIT(7)
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+#define CONFIG_BOOT_MODE_BIT BIT(6)
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+#define CONFIG_ADDR_AUTO_INCR_BIT BIT(5)
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+#define CONFIG_BUFNO_AUTO_INCR_BIT BIT(4)
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+#define CONFIG_PAGE_CNT_MASK 0xF
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+#define CONFIG_PAGE_CNT_SHIFT 0
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+
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+/* NFC_IRQ_STATUS Field */
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+#define IDLE_IRQ_BIT BIT(29)
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+#define IDLE_EN_BIT BIT(20)
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+#define CMD_DONE_CLEAR_BIT BIT(18)
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+#define IDLE_CLEAR_BIT BIT(17)
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+
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+enum vf610_nfc_alt_buf {
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+ ALT_BUF_DATA = 0,
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+ ALT_BUF_ID = 1,
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+ ALT_BUF_STAT = 2,
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+ ALT_BUF_ONFI = 3,
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+};
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+
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+enum vf610_nfc_variant {
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+ NFC_VFC610 = 1,
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+};
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+
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+struct vf610_nfc {
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+ struct mtd_info mtd;
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+ struct nand_chip chip;
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+ struct device *dev;
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+ void __iomem *regs;
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+ struct completion cmd_done;
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+ uint buf_offset;
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+ int write_sz;
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+ /* Status and ID are in alternate locations. */
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+ enum vf610_nfc_alt_buf alt_buf;
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+ enum vf610_nfc_variant variant;
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+ struct clk *clk;
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+};
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+
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+#define mtd_to_nfc(_mtd) container_of(_mtd, struct vf610_nfc, mtd)
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+
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+static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg)
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+{
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+ return readl(nfc->regs + reg);
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+}
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+
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+static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val)
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+{
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+ writel(val, nfc->regs + reg);
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+}
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+
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+static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits)
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+{
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+ vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits);
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+}
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+
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+static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits)
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+{
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+ vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits);
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+}
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+
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+static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg,
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+ u32 mask, u32 shift, u32 val)
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+{
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+ vf610_nfc_write(nfc, reg,
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+ (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift);
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+}
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+
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+static inline void vf610_nfc_memcpy(void *dst, const void __iomem *src,
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+ size_t n)
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+{
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+ /*
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+ * Use this accessor for the internal SRAM buffers. On the ARM
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+ * Freescale Vybrid SoC it's known that the driver can treat
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+ * the SRAM buffer as if it's memory. Other platform might need
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+ * to treat the buffers differently.
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+ *
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+ * For the time being, use memcpy
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+ */
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+ memcpy(dst, src, n);
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+}
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+
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+/* Clear flags for upcoming command */
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+static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc)
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+{
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+ u32 tmp = vf610_nfc_read(nfc, NFC_IRQ_STATUS);
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+
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+ tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
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+ vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp);
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+}
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+
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+static void vf610_nfc_done(struct vf610_nfc *nfc)
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+{
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+ unsigned long timeout = msecs_to_jiffies(100);
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+
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+ /*
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+ * Barrier is needed after this write. This write need
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+ * to be done before reading the next register the first
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+ * time.
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+ * vf610_nfc_set implicates such a barrier by using writel
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+ * to write to the register.
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+ */
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+ vf610_nfc_set(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
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+ vf610_nfc_set(nfc, NFC_FLASH_CMD2, START_BIT);
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+
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+ if (!wait_for_completion_timeout(&nfc->cmd_done, timeout))
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+ dev_warn(nfc->dev, "Timeout while waiting for BUSY.\n");
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+
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+ vf610_nfc_clear_status(nfc);
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+}
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+
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+static u8 vf610_nfc_get_id(struct vf610_nfc *nfc, int col)
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+{
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+ u32 flash_id;
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+
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+ if (col < 4) {
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+ flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS1);
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+ flash_id >>= (3 - col) * 8;
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+ } else {
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+ flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS2);
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+ flash_id >>= 24;
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+ }
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+
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+ return flash_id & 0xff;
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+}
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+
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+static u8 vf610_nfc_get_status(struct vf610_nfc *nfc)
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+{
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+ return vf610_nfc_read(nfc, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
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+}
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+
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+static void vf610_nfc_send_command(struct vf610_nfc *nfc, u32 cmd_byte1,
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+ u32 cmd_code)
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+{
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+ u32 tmp;
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+
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+ vf610_nfc_clear_status(nfc);
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+
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+ tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD2);
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+ tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
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+ tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
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+ tmp |= cmd_code << CMD_CODE_SHIFT;
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+ vf610_nfc_write(nfc, NFC_FLASH_CMD2, tmp);
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+}
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+
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+static void vf610_nfc_send_commands(struct vf610_nfc *nfc, u32 cmd_byte1,
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+ u32 cmd_byte2, u32 cmd_code)
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+{
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+ u32 tmp;
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+
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+ vf610_nfc_send_command(nfc, cmd_byte1, cmd_code);
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+
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+ tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD1);
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+ tmp &= ~CMD_BYTE2_MASK;
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+ tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
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+ vf610_nfc_write(nfc, NFC_FLASH_CMD1, tmp);
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+}
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+
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+static irqreturn_t vf610_nfc_irq(int irq, void *data)
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+{
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+ struct mtd_info *mtd = data;
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+ struct vf610_nfc *nfc = mtd_to_nfc(mtd);
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+
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+ vf610_nfc_clear(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
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+ complete(&nfc->cmd_done);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static void vf610_nfc_addr_cycle(struct vf610_nfc *nfc, int column, int page)
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+{
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+ if (column != -1) {
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+ if (nfc->chip.options & NAND_BUSWIDTH_16)
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+ column = column / 2;
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+ vf610_nfc_set_field(nfc, NFC_COL_ADDR, COL_ADDR_MASK,
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+ COL_ADDR_SHIFT, column);
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+ }
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+ if (page != -1)
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+ vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK,
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+ ROW_ADDR_SHIFT, page);
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+}
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+
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+static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size)
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+{
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+ vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size);
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+}
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+
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+static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
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+ int column, int page)
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+{
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+ struct vf610_nfc *nfc = mtd_to_nfc(mtd);
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+ int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
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+
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+ nfc->buf_offset = max(column, 0);
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+ nfc->alt_buf = ALT_BUF_DATA;
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+
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+ switch (command) {
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+ case NAND_CMD_SEQIN:
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+ /* Use valid column/page from preread... */
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+ vf610_nfc_addr_cycle(nfc, column, page);
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+ /*
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+ * SEQIN => data => PAGEPROG sequence is done by the controller
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+ * hence we do not need to issue the command here...
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+ */
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+ return;
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+ case NAND_CMD_PAGEPROG:
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+ trfr_sz += nfc->write_sz;
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+ vf610_nfc_transfer_size(nfc, trfr_sz);
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+ vf610_nfc_send_commands(nfc, NAND_CMD_SEQIN,
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+ command, PROGRAM_PAGE_CMD_CODE);
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+ break;
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+
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+ case NAND_CMD_RESET:
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+ vf610_nfc_transfer_size(nfc, 0);
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+ vf610_nfc_send_command(nfc, command, RESET_CMD_CODE);
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+ break;
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+
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+ case NAND_CMD_READOOB:
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+ trfr_sz += mtd->oobsize;
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+ column = mtd->writesize;
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+ vf610_nfc_transfer_size(nfc, trfr_sz);
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+ vf610_nfc_send_commands(nfc, NAND_CMD_READ0,
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+ NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
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+ vf610_nfc_addr_cycle(nfc, column, page);
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+ break;
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+
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+ case NAND_CMD_READ0:
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+ trfr_sz += mtd->writesize + mtd->oobsize;
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+ vf610_nfc_transfer_size(nfc, trfr_sz);
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+ vf610_nfc_send_commands(nfc, NAND_CMD_READ0,
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+ NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
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+ vf610_nfc_addr_cycle(nfc, column, page);
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+ break;
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+
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+ case NAND_CMD_PARAM:
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+ nfc->alt_buf = ALT_BUF_ONFI;
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+ trfr_sz = 3 * sizeof(struct nand_onfi_params);
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+ vf610_nfc_transfer_size(nfc, trfr_sz);
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+ vf610_nfc_send_command(nfc, command, READ_ONFI_PARAM_CMD_CODE);
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+ vf610_nfc_addr_cycle(nfc, -1, column);
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+ break;
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+
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+ case NAND_CMD_ERASE1:
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+ vf610_nfc_transfer_size(nfc, 0);
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+ vf610_nfc_send_commands(nfc, command,
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+ NAND_CMD_ERASE2, ERASE_CMD_CODE);
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+ vf610_nfc_addr_cycle(nfc, column, page);
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+ break;
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+
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+ case NAND_CMD_READID:
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+ nfc->alt_buf = ALT_BUF_ID;
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+ nfc->buf_offset = 0;
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+ vf610_nfc_transfer_size(nfc, 0);
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+ vf610_nfc_send_command(nfc, command, READ_ID_CMD_CODE);
|
|
|
+ vf610_nfc_addr_cycle(nfc, -1, column);
|
|
|
+ break;
|
|
|
+
|
|
|
+ case NAND_CMD_STATUS:
|
|
|
+ nfc->alt_buf = ALT_BUF_STAT;
|
|
|
+ vf610_nfc_transfer_size(nfc, 0);
|
|
|
+ vf610_nfc_send_command(nfc, command, STATUS_READ_CMD_CODE);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ vf610_nfc_done(nfc);
|
|
|
+
|
|
|
+ nfc->write_sz = 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
|
|
+{
|
|
|
+ struct vf610_nfc *nfc = mtd_to_nfc(mtd);
|
|
|
+ uint c = nfc->buf_offset;
|
|
|
+
|
|
|
+ /* Alternate buffers are only supported through read_byte */
|
|
|
+ WARN_ON(nfc->alt_buf);
|
|
|
+
|
|
|
+ vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
|
|
|
+
|
|
|
+ nfc->buf_offset += len;
|
|
|
+}
|
|
|
+
|
|
|
+static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
|
|
|
+ int len)
|
|
|
+{
|
|
|
+ struct vf610_nfc *nfc = mtd_to_nfc(mtd);
|
|
|
+ uint c = nfc->buf_offset;
|
|
|
+ uint l;
|
|
|
+
|
|
|
+ l = min_t(uint, len, mtd->writesize + mtd->oobsize - c);
|
|
|
+ vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
|
|
|
+
|
|
|
+ nfc->write_sz += l;
|
|
|
+ nfc->buf_offset += l;
|
|
|
+}
|
|
|
+
|
|
|
+static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd)
|
|
|
+{
|
|
|
+ struct vf610_nfc *nfc = mtd_to_nfc(mtd);
|
|
|
+ u8 tmp;
|
|
|
+ uint c = nfc->buf_offset;
|
|
|
+
|
|
|
+ switch (nfc->alt_buf) {
|
|
|
+ case ALT_BUF_ID:
|
|
|
+ tmp = vf610_nfc_get_id(nfc, c);
|
|
|
+ break;
|
|
|
+ case ALT_BUF_STAT:
|
|
|
+ tmp = vf610_nfc_get_status(nfc);
|
|
|
+ break;
|
|
|
+#ifdef __LITTLE_ENDIAN
|
|
|
+ case ALT_BUF_ONFI:
|
|
|
+ /* Reverse byte since the controller uses big endianness */
|
|
|
+ c = nfc->buf_offset ^ 0x3;
|
|
|
+ /* fall-through */
|
|
|
+#endif
|
|
|
+ default:
|
|
|
+ tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ nfc->buf_offset++;
|
|
|
+ return tmp;
|
|
|
+}
|
|
|
+
|
|
|
+static u16 vf610_nfc_read_word(struct mtd_info *mtd)
|
|
|
+{
|
|
|
+ u16 tmp;
|
|
|
+
|
|
|
+ vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
|
|
|
+ return tmp;
|
|
|
+}
|
|
|
+
|
|
|
+/* If not provided, upper layers apply a fixed delay. */
|
|
|
+static int vf610_nfc_dev_ready(struct mtd_info *mtd)
|
|
|
+{
|
|
|
+ /* NFC handles R/B internally; always ready. */
|
|
|
+ return 1;
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * This function supports Vybrid only (MPC5125 would have full RB and four CS)
|
|
|
+ */
|
|
|
+static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
|
|
|
+{
|
|
|
+ struct vf610_nfc *nfc = mtd_to_nfc(mtd);
|
|
|
+ u32 tmp = vf610_nfc_read(nfc, NFC_ROW_ADDR);
|
|
|
+
|
|
|
+ /* Vybrid only (MPC5125 would have full RB and four CS) */
|
|
|
+ if (nfc->variant != NFC_VFC610)
|
|
|
+ return;
|
|
|
+
|
|
|
+ tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
|
|
|
+
|
|
|
+ if (chip >= 0) {
|
|
|
+ tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
|
|
|
+ tmp |= BIT(chip) << ROW_ADDR_CHIP_SEL_SHIFT;
|
|
|
+ }
|
|
|
+
|
|
|
+ vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp);
|
|
|
+}
|
|
|
+
|
|
|
+static const struct of_device_id vf610_nfc_dt_ids[] = {
|
|
|
+ { .compatible = "fsl,vf610-nfc", .data = (void *)NFC_VFC610 },
|
|
|
+ { /* sentinel */ }
|
|
|
+};
|
|
|
+MODULE_DEVICE_TABLE(of, vf610_nfc_dt_ids);
|
|
|
+
|
|
|
+static void vf610_nfc_preinit_controller(struct vf610_nfc *nfc)
|
|
|
+{
|
|
|
+ vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
|
|
|
+ vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
|
|
|
+ vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
|
|
|
+ vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
|
|
|
+ vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
|
|
|
+ vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
|
|
|
+
|
|
|
+ /* Disable virtual pages, only one elementary transfer unit */
|
|
|
+ vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
|
|
|
+ CONFIG_PAGE_CNT_SHIFT, 1);
|
|
|
+}
|
|
|
+
|
|
|
+static void vf610_nfc_init_controller(struct vf610_nfc *nfc)
|
|
|
+{
|
|
|
+ if (nfc->chip.options & NAND_BUSWIDTH_16)
|
|
|
+ vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
|
|
|
+ else
|
|
|
+ vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
|
|
|
+}
|
|
|
+
|
|
|
+static int vf610_nfc_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct vf610_nfc *nfc;
|
|
|
+ struct resource *res;
|
|
|
+ struct mtd_info *mtd;
|
|
|
+ struct nand_chip *chip;
|
|
|
+ struct device_node *child;
|
|
|
+ const struct of_device_id *of_id;
|
|
|
+ int err;
|
|
|
+ int irq;
|
|
|
+
|
|
|
+ nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
|
|
|
+ if (!nfc)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ nfc->dev = &pdev->dev;
|
|
|
+ mtd = &nfc->mtd;
|
|
|
+ chip = &nfc->chip;
|
|
|
+
|
|
|
+ mtd->priv = chip;
|
|
|
+ mtd->owner = THIS_MODULE;
|
|
|
+ mtd->dev.parent = nfc->dev;
|
|
|
+ mtd->name = DRV_NAME;
|
|
|
+
|
|
|
+ irq = platform_get_irq(pdev, 0);
|
|
|
+ if (irq <= 0)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
+ nfc->regs = devm_ioremap_resource(nfc->dev, res);
|
|
|
+ if (IS_ERR(nfc->regs))
|
|
|
+ return PTR_ERR(nfc->regs);
|
|
|
+
|
|
|
+ nfc->clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
+ if (IS_ERR(nfc->clk))
|
|
|
+ return PTR_ERR(nfc->clk);
|
|
|
+
|
|
|
+ err = clk_prepare_enable(nfc->clk);
|
|
|
+ if (err) {
|
|
|
+ dev_err(nfc->dev, "Unable to enable clock!\n");
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
+ of_id = of_match_device(vf610_nfc_dt_ids, &pdev->dev);
|
|
|
+ nfc->variant = (enum vf610_nfc_variant)of_id->data;
|
|
|
+
|
|
|
+ for_each_available_child_of_node(nfc->dev->of_node, child) {
|
|
|
+ if (of_device_is_compatible(child, "fsl,vf610-nfc-nandcs")) {
|
|
|
+
|
|
|
+ if (chip->flash_node) {
|
|
|
+ dev_err(nfc->dev,
|
|
|
+ "Only one NAND chip supported!\n");
|
|
|
+ err = -EINVAL;
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+
|
|
|
+ chip->flash_node = child;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!chip->flash_node) {
|
|
|
+ dev_err(nfc->dev, "NAND chip sub-node missing!\n");
|
|
|
+ err = -ENODEV;
|
|
|
+ goto err_clk;
|
|
|
+ }
|
|
|
+
|
|
|
+ chip->dev_ready = vf610_nfc_dev_ready;
|
|
|
+ chip->cmdfunc = vf610_nfc_command;
|
|
|
+ chip->read_byte = vf610_nfc_read_byte;
|
|
|
+ chip->read_word = vf610_nfc_read_word;
|
|
|
+ chip->read_buf = vf610_nfc_read_buf;
|
|
|
+ chip->write_buf = vf610_nfc_write_buf;
|
|
|
+ chip->select_chip = vf610_nfc_select_chip;
|
|
|
+
|
|
|
+ chip->options |= NAND_NO_SUBPAGE_WRITE;
|
|
|
+
|
|
|
+ init_completion(&nfc->cmd_done);
|
|
|
+
|
|
|
+ err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, mtd);
|
|
|
+ if (err) {
|
|
|
+ dev_err(nfc->dev, "Error requesting IRQ!\n");
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+
|
|
|
+ vf610_nfc_preinit_controller(nfc);
|
|
|
+
|
|
|
+ /* first scan to find the device and get the page size */
|
|
|
+ if (nand_scan_ident(mtd, 1, NULL)) {
|
|
|
+ err = -ENXIO;
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+
|
|
|
+ vf610_nfc_init_controller(nfc);
|
|
|
+
|
|
|
+ /* Bad block options. */
|
|
|
+ if (chip->bbt_options & NAND_BBT_USE_FLASH)
|
|
|
+ chip->bbt_options |= NAND_BBT_NO_OOB;
|
|
|
+
|
|
|
+ /* Single buffer only, max 256 OOB minus ECC status */
|
|
|
+ if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
|
|
|
+ dev_err(nfc->dev, "Unsupported flash page size\n");
|
|
|
+ err = -ENXIO;
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* second phase scan */
|
|
|
+ if (nand_scan_tail(mtd)) {
|
|
|
+ err = -ENXIO;
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+
|
|
|
+ platform_set_drvdata(pdev, mtd);
|
|
|
+
|
|
|
+ /* Register device in MTD */
|
|
|
+ return mtd_device_parse_register(mtd, NULL,
|
|
|
+ &(struct mtd_part_parser_data){
|
|
|
+ .of_node = chip->flash_node,
|
|
|
+ },
|
|
|
+ NULL, 0);
|
|
|
+
|
|
|
+error:
|
|
|
+ of_node_put(chip->flash_node);
|
|
|
+err_clk:
|
|
|
+ clk_disable_unprepare(nfc->clk);
|
|
|
+ return err;
|
|
|
+}
|
|
|
+
|
|
|
+static int vf610_nfc_remove(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct mtd_info *mtd = platform_get_drvdata(pdev);
|
|
|
+ struct vf610_nfc *nfc = mtd_to_nfc(mtd);
|
|
|
+
|
|
|
+ nand_release(mtd);
|
|
|
+ clk_disable_unprepare(nfc->clk);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
|
+static int vf610_nfc_suspend(struct device *dev)
|
|
|
+{
|
|
|
+ struct mtd_info *mtd = dev_get_drvdata(dev);
|
|
|
+ struct vf610_nfc *nfc = mtd_to_nfc(mtd);
|
|
|
+
|
|
|
+ clk_disable_unprepare(nfc->clk);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int vf610_nfc_resume(struct device *dev)
|
|
|
+{
|
|
|
+ struct mtd_info *mtd = dev_get_drvdata(dev);
|
|
|
+ struct vf610_nfc *nfc = mtd_to_nfc(mtd);
|
|
|
+
|
|
|
+ pinctrl_pm_select_default_state(dev);
|
|
|
+
|
|
|
+ clk_prepare_enable(nfc->clk);
|
|
|
+
|
|
|
+ vf610_nfc_preinit_controller(nfc);
|
|
|
+ vf610_nfc_init_controller(nfc);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops, vf610_nfc_suspend, vf610_nfc_resume);
|
|
|
+
|
|
|
+static struct platform_driver vf610_nfc_driver = {
|
|
|
+ .driver = {
|
|
|
+ .name = DRV_NAME,
|
|
|
+ .of_match_table = vf610_nfc_dt_ids,
|
|
|
+ .pm = &vf610_nfc_pm_ops,
|
|
|
+ },
|
|
|
+ .probe = vf610_nfc_probe,
|
|
|
+ .remove = vf610_nfc_remove,
|
|
|
+};
|
|
|
+
|
|
|
+module_platform_driver(vf610_nfc_driver);
|
|
|
+
|
|
|
+MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>");
|
|
|
+MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver");
|
|
|
+MODULE_LICENSE("GPL");
|
Stefan Agner