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@@ -103,6 +103,7 @@
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#define CORE_DDR_200_CFG 0x184
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#define CORE_CDC_T4_DLY_SEL BIT(0)
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+#define CORE_CMDIN_RCLK_EN BIT(1)
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#define CORE_START_CDC_TRAFFIC BIT(6)
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#define CORE_VENDOR_SPEC3 0x1b0
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#define CORE_PWRSAVE_DLL BIT(3)
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@@ -547,6 +548,7 @@ static void msm_hc_select_hs400(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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+ struct mmc_ios ios = host->mmc->ios;
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u32 config, dll_lock;
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int rc;
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@@ -560,7 +562,8 @@ static void msm_hc_select_hs400(struct sdhci_host *host)
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* Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
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* register
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*/
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- if (msm_host->tuning_done && !msm_host->calibration_done) {
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+ if ((msm_host->tuning_done || ios.enhanced_strobe) &&
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+ !msm_host->calibration_done) {
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config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
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config |= CORE_HC_SELECT_IN_HS400;
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config |= CORE_HC_SELECT_IN_EN;
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@@ -734,6 +737,7 @@ out:
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static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
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{
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+ struct mmc_host *mmc = host->mmc;
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u32 dll_status, config;
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int ret;
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@@ -748,6 +752,12 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
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*/
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writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
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+ if (mmc->ios.enhanced_strobe) {
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+ config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
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+ config |= CORE_CMDIN_RCLK_EN;
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+ writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
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+ }
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+
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config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
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config |= CORE_DDR_CAL_EN;
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writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
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@@ -782,6 +792,7 @@ static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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+ struct mmc_host *mmc = host->mmc;
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int ret;
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u32 config;
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@@ -795,14 +806,17 @@ static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
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if (ret)
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goto out;
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- /* Set the selected phase in delay line hw block */
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- ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
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- if (ret)
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- goto out;
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+ if (!mmc->ios.enhanced_strobe) {
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+ /* Set the selected phase in delay line hw block */
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+ ret = msm_config_cm_dll_phase(host,
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+ msm_host->saved_tuning_phase);
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+ if (ret)
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+ goto out;
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+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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+ config |= CORE_CMD_DAT_TRACK_SEL;
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+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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+ }
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- config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
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- config |= CORE_CMD_DAT_TRACK_SEL;
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- writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
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if (msm_host->use_cdclp533)
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ret = sdhci_msm_cdclp533_calibration(host);
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else
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@@ -899,6 +913,7 @@ retry:
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/*
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* sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
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+ * This needs to be done for both tuning and enhanced_strobe mode.
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* DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
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* fixed feedback clock is used.
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*/
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@@ -909,7 +924,8 @@ static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
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int ret;
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if (host->clock > CORE_FREQ_100MHZ &&
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- msm_host->tuning_done && !msm_host->calibration_done) {
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+ (msm_host->tuning_done || ios->enhanced_strobe) &&
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+ !msm_host->calibration_done) {
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ret = sdhci_msm_hs400_dll_calibration(host);
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if (!ret)
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msm_host->calibration_done = true;
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