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+Microsemi Ocelot network Switch
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+===============================
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+
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+The Microsemi Ocelot network switch can be found on Microsemi SoCs (VSC7513,
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+VSC7514)
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+
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+Required properties:
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+- compatible: Should be "mscc,vsc7514-switch"
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+- reg: Must contain an (offset, length) pair of the register set for each
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+ entry in reg-names.
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+- reg-names: Must include the following entries:
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+ - "sys"
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+ - "rew"
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+ - "qs"
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+ - "hsio"
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+ - "qsys"
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+ - "ana"
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+ - "portX" with X from 0 to the number of last port index available on that
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+ switch
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+- interrupts: Should contain the switch interrupts for frame extraction and
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+ frame injection
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+- interrupt-names: should contain the interrupt names: "xtr", "inj"
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+- ethernet-ports: A container for child nodes representing switch ports.
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+
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+The ethernet-ports container has the following properties
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+
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+Required properties:
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+
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+- #address-cells: Must be 1
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+- #size-cells: Must be 0
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+
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+Each port node must have the following mandatory properties:
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+- reg: Describes the port address in the switch
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+
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+Port nodes may also contain the following optional standardised
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+properties, described in binding documents:
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+
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+- phy-handle: Phandle to a PHY on an MDIO bus. See
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+ Documentation/devicetree/bindings/net/ethernet.txt for details.
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+
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+Example:
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+
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+ switch@1010000 {
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+ compatible = "mscc,vsc7514-switch";
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+ reg = <0x1010000 0x10000>,
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+ <0x1030000 0x10000>,
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+ <0x1080000 0x100>,
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+ <0x10d0000 0x10000>,
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+ <0x11e0000 0x100>,
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+ <0x11f0000 0x100>,
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+ <0x1200000 0x100>,
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+ <0x1210000 0x100>,
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+ <0x1220000 0x100>,
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+ <0x1230000 0x100>,
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+ <0x1240000 0x100>,
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+ <0x1250000 0x100>,
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+ <0x1260000 0x100>,
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+ <0x1270000 0x100>,
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+ <0x1280000 0x100>,
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+ <0x1800000 0x80000>,
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+ <0x1880000 0x10000>;
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+ reg-names = "sys", "rew", "qs", "hsio", "port0",
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+ "port1", "port2", "port3", "port4", "port5",
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+ "port6", "port7", "port8", "port9", "port10",
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+ "qsys", "ana";
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+ interrupts = <21 22>;
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+ interrupt-names = "xtr", "inj";
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+
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+ ethernet-ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port0: port@0 {
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+ reg = <0>;
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+ phy-handle = <&phy0>;
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+ };
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+ port1: port@1 {
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+ reg = <1>;
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+ phy-handle = <&phy1>;
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+ };
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+ };
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+ };
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