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@@ -981,7 +981,7 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct tegra_clk_pll_freq_table cfg, old_cfg;
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unsigned long flags = 0;
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- int ret = 0;
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+ int ret;
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ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
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if (ret < 0)
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@@ -1005,7 +1005,7 @@ static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct tegra_clk_pll_freq_table cfg;
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- int ret = 0, p_div;
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+ int ret, p_div;
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u64 output_rate = *prate;
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ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
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@@ -1073,7 +1073,7 @@ static int clk_pllc_enable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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u32 val;
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- int ret = 0;
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+ int ret;
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unsigned long flags = 0;
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if (pll->lock)
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