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@@ -291,6 +291,14 @@ static const struct clockgen_muxinfo ls1046a_hwa2 = {
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},
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};
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+static const struct clockgen_muxinfo ls1012a_cmux = {
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+ {
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+ [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
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+ {},
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+ [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
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+ }
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+};
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+
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static const struct clockgen_muxinfo t1023_hwa1 = {
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{
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{},
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@@ -528,6 +536,16 @@ static const struct clockgen_chipinfo chipinfo[] = {
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.pll_mask = 0x07,
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.flags = CG_PLL_8BIT,
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},
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+ {
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+ .compat = "fsl,ls1012a-clockgen",
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+ .cmux_groups = {
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+ &ls1012a_cmux
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+ },
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+ .cmux_to_group = {
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+ 0, -1
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+ },
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+ .pll_mask = 0x03,
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+ },
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{
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.compat = "fsl,ls2080a-clockgen",
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.cmux_groups = {
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@@ -1313,6 +1331,7 @@ err:
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CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
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+CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
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