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@@ -270,14 +270,13 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
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static void amd_threshold_interrupt(void)
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{
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u32 low = 0, high = 0, address = 0;
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+ int cpu = smp_processor_id();
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unsigned int bank, block;
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struct mce m;
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- mce_setup(&m);
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-
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/* assume first bank caused it */
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for (bank = 0; bank < mca_cfg.banks; ++bank) {
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- if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
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+ if (!(per_cpu(bank_map, cpu) & (1 << bank)))
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continue;
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for (block = 0; block < NR_BLOCKS; ++block) {
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if (block == 0) {
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@@ -309,20 +308,21 @@ static void amd_threshold_interrupt(void)
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* Log the machine check that caused the threshold
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* event.
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*/
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- machine_check_poll(MCP_TIMESTAMP,
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- this_cpu_ptr(&mce_poll_banks));
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-
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- if (high & MASK_OVERFLOW_HI) {
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- rdmsrl(address, m.misc);
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- rdmsrl(MSR_IA32_MCx_STATUS(bank), m.status);
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- m.bank = K8_MCE_THRESHOLD_BASE
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- + bank * NR_BLOCKS
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- + block;
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- mce_log(&m);
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- return;
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- }
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+ if (high & MASK_OVERFLOW_HI)
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+ goto log;
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}
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}
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+ return;
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+
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+log:
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+ mce_setup(&m);
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+ rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
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+ rdmsrl(address, m.misc);
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+ rdmsrl(MSR_IA32_MCx_STATUS(bank), m.status);
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+ m.bank = K8_MCE_THRESHOLD_BASE + bank * NR_BLOCKS + block;
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+ mce_log(&m);
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+
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+ wrmsrl(MSR_IA32_MCx_STATUS(bank), 0);
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}
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/*
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