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@@ -880,6 +880,22 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
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vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
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}
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+static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
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+ uint32_t reg, uint32_t val)
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+{
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+ struct amdgpu_device *adev = ring->adev;
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+
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+ amdgpu_ring_write(ring,
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+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
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+ amdgpu_ring_write(ring, reg << 2);
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+ amdgpu_ring_write(ring,
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+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
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+ amdgpu_ring_write(ring, val);
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+ amdgpu_ring_write(ring,
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+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
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+ amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
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+}
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+
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/**
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* vcn_v1_0_enc_ring_get_rptr - get enc read pointer
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*
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@@ -1097,7 +1113,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.begin_use = amdgpu_vcn_ring_begin_use,
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.end_use = amdgpu_vcn_ring_end_use,
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- .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
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+ .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
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};
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static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
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@@ -1124,6 +1140,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.begin_use = amdgpu_vcn_ring_begin_use,
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.end_use = amdgpu_vcn_ring_end_use,
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+ .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
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};
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static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
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