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@@ -29,7 +29,7 @@
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#define CLK_PLL_AUDIO_4X 6
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#define CLK_PLL_AUDIO_8X 7
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#define CLK_PLL_VIDEO0 8
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-#define CLK_PLL_VIDEO0_2X 9
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+/* The PLL_VIDEO0_2X clock is exported */
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#define CLK_PLL_VE 10
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#define CLK_PLL_DDR_BASE 11
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#define CLK_PLL_DDR 12
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@@ -38,7 +38,7 @@
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#define CLK_PLL_PERIPH 15
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#define CLK_PLL_PERIPH_SATA 16
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#define CLK_PLL_VIDEO1 17
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-#define CLK_PLL_VIDEO1_2X 18
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+/* The PLL_VIDEO1_2X clock is exported */
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#define CLK_PLL_GPU 19
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/* The CPU clock is exported */
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