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@@ -137,7 +137,7 @@ void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
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* other fields
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*/
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- ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
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+ ah->wow.wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
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if (pattern_count < 4) {
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/* Pattern 0-3 uses AR_WOW_LENGTH1 register */
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@@ -174,7 +174,7 @@ u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
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* register. This mask will clean it up.
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*/
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- val &= ah->wow_event_mask;
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+ val &= ah->wow.wow_event_mask;
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if (val) {
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if (val & AR_WOW_MAGIC_PAT_FOUND)
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@@ -218,7 +218,7 @@ u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
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if (ah->is_pciexpress)
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ath9k_hw_configpcipowersave(ah, false);
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- ah->wow_event_mask = 0;
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+ ah->wow.wow_event_mask = 0;
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return wow_status;
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}
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@@ -235,7 +235,7 @@ void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
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* are from the 'pattern_enable' in this function and
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* 'pattern_count' of ath9k_hw_wow_apply_pattern()
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*/
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- wow_event_mask = ah->wow_event_mask;
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+ wow_event_mask = ah->wow.wow_event_mask;
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/*
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* Untie Power-on-Reset from the PCI-E-Reset. When we are in
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@@ -402,6 +402,6 @@ void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
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REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
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ath9k_hw_set_powermode_wow_sleep(ah);
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- ah->wow_event_mask = wow_event_mask;
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+ ah->wow.wow_event_mask = wow_event_mask;
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}
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EXPORT_SYMBOL(ath9k_hw_wow_enable);
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