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@@ -0,0 +1,189 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * AM33XX Arch Power Management Routines
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+ *
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+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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+ * Dave Gerlach
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+ */
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+
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+#include <asm/smp_scu.h>
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+#include <asm/suspend.h>
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+#include <linux/errno.h>
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+#include <linux/platform_data/pm33xx.h>
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+
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+#include "cm33xx.h"
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+#include "common.h"
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+#include "control.h"
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+#include "clockdomain.h"
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+#include "iomap.h"
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+#include "omap_hwmod.h"
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+#include "pm.h"
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+#include "powerdomain.h"
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+#include "prm33xx.h"
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+#include "soc.h"
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+#include "sram.h"
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+
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+static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
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+static struct clockdomain *gfx_l4ls_clkdm;
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+static void __iomem *scu_base;
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+
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+static int __init am43xx_map_scu(void)
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+{
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+ scu_base = ioremap(scu_a9_get_base(), SZ_256);
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+
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+ if (!scu_base)
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+ return -ENOMEM;
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+
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+ return 0;
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+}
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+
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+static int amx3_common_init(void)
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+{
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+ gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
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+ per_pwrdm = pwrdm_lookup("per_pwrdm");
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+ mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
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+
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+ if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm))
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+ return -ENODEV;
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+
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+ (void)clkdm_for_each(omap_pm_clkdms_setup, NULL);
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+
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+ /* CEFUSE domain can be turned off post bootup */
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+ cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
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+ if (cefuse_pwrdm)
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+ omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
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+ else
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+ pr_err("PM: Failed to get cefuse_pwrdm\n");
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+
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+ return 0;
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+}
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+
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+static int am33xx_suspend_init(void)
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+{
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+ int ret;
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+
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+ gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
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+
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+ if (!gfx_l4ls_clkdm) {
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+ pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n");
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+ return -ENODEV;
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+ }
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+
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+ ret = amx3_common_init();
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+
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+ return ret;
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+}
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+
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+static int am43xx_suspend_init(void)
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+{
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+ int ret = 0;
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+
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+ ret = am43xx_map_scu();
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+ if (ret) {
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+ pr_err("PM: Could not ioremap SCU\n");
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+ return ret;
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+ }
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+
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+ ret = amx3_common_init();
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+
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+ return ret;
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+}
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+
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+static void amx3_pre_suspend_common(void)
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+{
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+ omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF);
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+}
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+
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+static void amx3_post_suspend_common(void)
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+{
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+ int status;
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+ /*
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+ * Because gfx_pwrdm is the only one under MPU control,
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+ * comment on transition status
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+ */
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+ status = pwrdm_read_pwrst(gfx_pwrdm);
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+ if (status != PWRDM_POWER_OFF)
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+ pr_err("PM: GFX domain did not transition: %x\n", status);
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+}
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+
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+static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long))
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+{
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+ int ret = 0;
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+
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+ amx3_pre_suspend_common();
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+ ret = cpu_suspend(0, fn);
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+ amx3_post_suspend_common();
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+
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+ /*
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+ * BUG: GFX_L4LS clock domain needs to be woken up to
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+ * ensure thet L4LS clock domain does not get stuck in
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+ * transition. If that happens L3 module does not get
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+ * disabled, thereby leading to PER power domain
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+ * transition failing
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+ */
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+
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+ clkdm_wakeup(gfx_l4ls_clkdm);
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+ clkdm_sleep(gfx_l4ls_clkdm);
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+
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+ return ret;
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+}
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+
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+static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long))
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+{
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+ int ret = 0;
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+
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+ amx3_pre_suspend_common();
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+ scu_power_mode(scu_base, SCU_PM_POWEROFF);
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+ ret = cpu_suspend(0, fn);
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+ scu_power_mode(scu_base, SCU_PM_NORMAL);
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+ amx3_post_suspend_common();
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+
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+ return ret;
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+}
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+
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+static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void)
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+{
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+ if (soc_is_am33xx())
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+ return &am33xx_pm_sram;
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+ else if (soc_is_am437x())
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+ return &am43xx_pm_sram;
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+ else
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+ return NULL;
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+}
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+
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+static struct am33xx_pm_platform_data am33xx_ops = {
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+ .init = am33xx_suspend_init,
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+ .soc_suspend = am33xx_suspend,
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+ .get_sram_addrs = amx3_get_sram_addrs,
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+};
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+
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+static struct am33xx_pm_platform_data am43xx_ops = {
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+ .init = am43xx_suspend_init,
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+ .soc_suspend = am43xx_suspend,
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+ .get_sram_addrs = amx3_get_sram_addrs,
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+};
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+
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+static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void)
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+{
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+ if (soc_is_am33xx())
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+ return &am33xx_ops;
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+ else if (soc_is_am437x())
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+ return &am43xx_ops;
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+ else
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+ return NULL;
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+}
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+
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+void __init amx3_common_pm_init(void)
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+{
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+ struct am33xx_pm_platform_data *pdata;
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+ struct platform_device_info devinfo;
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+
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+ pdata = am33xx_pm_get_pdata();
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+
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+ memset(&devinfo, 0, sizeof(devinfo));
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+ devinfo.name = "pm33xx";
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+ devinfo.data = pdata;
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+ devinfo.size_data = sizeof(*pdata);
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+ devinfo.id = -1;
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+ platform_device_register_full(&devinfo);
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+}
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