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@@ -639,6 +639,32 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
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else
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position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
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+ /*
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+ * On HSW, the DSL reg (0x70000) appears to return 0 if we
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+ * read it just before the start of vblank. So try it again
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+ * so we don't accidentally end up spanning a vblank frame
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+ * increment, causing the pipe_update_end() code to squak at us.
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+ *
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+ * The nature of this problem means we can't simply check the ISR
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+ * bit and return the vblank start value; nor can we use the scanline
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+ * debug register in the transcoder as it appears to have the same
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+ * problem. We may need to extend this to include other platforms,
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+ * but so far testing only shows the problem on HSW.
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+ */
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+ if (IS_HASWELL(dev) && !position) {
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+ int i, temp;
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+
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+ for (i = 0; i < 100; i++) {
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+ udelay(1);
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+ temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
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+ DSL_LINEMASK_GEN3;
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+ if (temp != position) {
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+ position = temp;
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+ break;
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+ }
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+ }
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+ }
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+
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/*
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* See update_scanline_offset() for the details on the
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* scanline_offset adjustment.
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