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@@ -36,8 +36,6 @@
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#include <asm/apb_timer.h>
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#include <asm/apb_timer.h>
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#include <asm/reboot.h>
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#include <asm/reboot.h>
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-#include "intel_mid_weak_decls.h"
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-
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/*
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/*
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* the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
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* the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
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* cmdline option x86_intel_mid_timer can be used to override the configuration
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* cmdline option x86_intel_mid_timer can be used to override the configuration
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@@ -61,10 +59,6 @@
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enum intel_mid_timer_options intel_mid_timer_options;
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enum intel_mid_timer_options intel_mid_timer_options;
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-/* intel_mid_ops to store sub arch ops */
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-static struct intel_mid_ops *intel_mid_ops;
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-/* getter function for sub arch ops*/
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-static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;
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enum intel_mid_cpu_type __intel_mid_cpu_chip;
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enum intel_mid_cpu_type __intel_mid_cpu_chip;
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EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
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EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
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@@ -128,6 +122,7 @@ static void intel_mid_arch_setup(void)
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case 0x3C:
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case 0x3C:
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case 0x4A:
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case 0x4A:
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__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
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__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
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+ x86_platform.legacy.rtc = 1;
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break;
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break;
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case 0x27:
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case 0x27:
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default:
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default:
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@@ -135,17 +130,7 @@ static void intel_mid_arch_setup(void)
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break;
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break;
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}
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}
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- if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops))
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- intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
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- else {
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- intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
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- pr_info("ARCH: Unknown SoC, assuming Penwell!\n");
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- }
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-
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out:
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out:
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- if (intel_mid_ops->arch_setup)
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- intel_mid_ops->arch_setup();
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-
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/*
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/*
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* Intel MID platforms are using explicitly defined regulators.
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* Intel MID platforms are using explicitly defined regulators.
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*
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*
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