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@@ -4073,6 +4073,58 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst,
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sizeof(dst->ddb.plane[pipe]));
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}
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+static void
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+skl_print_wm_changes(const struct drm_atomic_state *state)
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+{
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+ const struct drm_device *dev = state->dev;
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+ const struct drm_i915_private *dev_priv = to_i915(dev);
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+ const struct intel_atomic_state *intel_state =
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+ to_intel_atomic_state(state);
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+ const struct drm_crtc *crtc;
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+ const struct drm_crtc_state *cstate;
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+ const struct drm_plane *plane;
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+ const struct intel_plane *intel_plane;
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+ const struct drm_plane_state *pstate;
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+ const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
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+ const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
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+ enum pipe pipe;
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+ int id;
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+ int i, j;
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+
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+ for_each_crtc_in_state(state, crtc, cstate, i) {
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+ pipe = to_intel_crtc(crtc)->pipe;
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+
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+ for_each_plane_in_state(state, plane, pstate, j) {
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+ const struct skl_ddb_entry *old, *new;
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+
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+ intel_plane = to_intel_plane(plane);
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+ id = skl_wm_plane_id(intel_plane);
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+ old = &old_ddb->plane[pipe][id];
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+ new = &new_ddb->plane[pipe][id];
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+
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+ if (intel_plane->pipe != pipe)
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+ continue;
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+
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+ if (skl_ddb_entry_equal(old, new))
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+ continue;
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+
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+ if (id != PLANE_CURSOR) {
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+ DRM_DEBUG_ATOMIC("[PLANE:%d:plane %d%c] ddb (%d - %d) -> (%d - %d)\n",
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+ plane->base.id, id + 1,
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+ pipe_name(pipe),
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+ old->start, old->end,
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+ new->start, new->end);
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+ } else {
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+ DRM_DEBUG_ATOMIC("[PLANE:%d:cursor %c] ddb (%d - %d) -> (%d - %d)\n",
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+ plane->base.id,
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+ pipe_name(pipe),
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+ old->start, old->end,
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+ new->start, new->end);
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+ }
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+ }
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+ }
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+}
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+
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static int
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skl_compute_wm(struct drm_atomic_state *state)
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{
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@@ -4134,6 +4186,8 @@ skl_compute_wm(struct drm_atomic_state *state)
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intel_cstate->update_wm_pre = true;
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}
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+ skl_print_wm_changes(state);
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+
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return 0;
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}
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