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@@ -66,7 +66,7 @@
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#define ADF_DH895XCC_ETR_MAX_BANKS 32
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#define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
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#define ADF_DH895XCC_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
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-#define ADF_DH895XCC_SMIA0_MASK 0xFFFF
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+#define ADF_DH895XCC_SMIA0_MASK 0xFFFFFFFF
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#define ADF_DH895XCC_SMIA1_MASK 0x1
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/* Error detection and correction */
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#define ADF_DH895XCC_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
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