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@@ -65,26 +65,25 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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cpu_data[n].watch_reg_masks[i]);
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seq_printf(m, "]\n");
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}
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- if (cpu_has_mips_r) {
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- seq_printf(m, "isa\t\t\t: mips1");
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- if (cpu_has_mips_2)
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- seq_printf(m, "%s", " mips2");
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- if (cpu_has_mips_3)
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- seq_printf(m, "%s", " mips3");
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- if (cpu_has_mips_4)
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- seq_printf(m, "%s", " mips4");
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- if (cpu_has_mips_5)
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- seq_printf(m, "%s", " mips5");
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- if (cpu_has_mips32r1)
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- seq_printf(m, "%s", " mips32r1");
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- if (cpu_has_mips32r2)
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- seq_printf(m, "%s", " mips32r2");
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- if (cpu_has_mips64r1)
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- seq_printf(m, "%s", " mips64r1");
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- if (cpu_has_mips64r2)
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- seq_printf(m, "%s", " mips64r2");
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- seq_printf(m, "\n");
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- }
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+
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+ seq_printf(m, "isa\t\t\t: mips1");
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+ if (cpu_has_mips_2)
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+ seq_printf(m, "%s", " mips2");
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+ if (cpu_has_mips_3)
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+ seq_printf(m, "%s", " mips3");
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+ if (cpu_has_mips_4)
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+ seq_printf(m, "%s", " mips4");
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+ if (cpu_has_mips_5)
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+ seq_printf(m, "%s", " mips5");
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+ if (cpu_has_mips32r1)
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+ seq_printf(m, "%s", " mips32r1");
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+ if (cpu_has_mips32r2)
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+ seq_printf(m, "%s", " mips32r2");
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+ if (cpu_has_mips64r1)
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+ seq_printf(m, "%s", " mips64r1");
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+ if (cpu_has_mips64r2)
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+ seq_printf(m, "%s", " mips64r2");
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+ seq_printf(m, "\n");
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seq_printf(m, "ASEs implemented\t:");
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if (cpu_has_mips16) seq_printf(m, "%s", " mips16");
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