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@@ -61,7 +61,8 @@
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#define TLP_LOOP 500
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#define RP_DEVFN 0
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-#define LINK_UP_TIMEOUT 5000
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+#define LINK_UP_TIMEOUT HZ
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+#define LINK_RETRAIN_TIMEOUT HZ
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#define INTX_NUM 4
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@@ -99,11 +100,44 @@ static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
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return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
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}
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+static void altera_wait_link_retrain(struct pci_dev *dev)
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+{
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+ u16 reg16;
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+ unsigned long start_jiffies;
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+ struct altera_pcie *pcie = dev->bus->sysdata;
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+
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+ /* Wait for link training end. */
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+ start_jiffies = jiffies;
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+ for (;;) {
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+ pcie_capability_read_word(dev, PCI_EXP_LNKSTA, ®16);
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+ if (!(reg16 & PCI_EXP_LNKSTA_LT))
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+ break;
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+
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+ if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
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+ dev_err(&pcie->pdev->dev, "link retrain timeout\n");
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+ break;
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+ }
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+ udelay(100);
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+ }
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+
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+ /* Wait for link is up */
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+ start_jiffies = jiffies;
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+ for (;;) {
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+ if (altera_pcie_link_is_up(pcie))
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+ break;
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+
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+ if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
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+ dev_err(&pcie->pdev->dev, "link up timeout\n");
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+ break;
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+ }
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+ udelay(100);
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+ }
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+}
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+
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static void altera_pcie_retrain(struct pci_dev *dev)
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{
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u16 linkcap, linkstat;
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struct altera_pcie *pcie = dev->bus->sysdata;
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- int timeout = 0;
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if (!altera_pcie_link_is_up(pcie))
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return;
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@@ -121,12 +155,7 @@ static void altera_pcie_retrain(struct pci_dev *dev)
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if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
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pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_RL);
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- while (!altera_pcie_link_is_up(pcie)) {
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- timeout++;
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- if (timeout > LINK_UP_TIMEOUT)
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- break;
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- udelay(5);
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- }
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+ altera_wait_link_retrain(dev);
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}
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}
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DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
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