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@@ -21,24 +21,24 @@
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/* i.MX1 and i.MX21 share the same PWM function block: */
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-#define MX1_PWMC 0x00 /* PWM Control Register */
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-#define MX1_PWMS 0x04 /* PWM Sample Register */
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-#define MX1_PWMP 0x08 /* PWM Period Register */
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+#define MX1_PWMC 0x00 /* PWM Control Register */
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+#define MX1_PWMS 0x04 /* PWM Sample Register */
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+#define MX1_PWMP 0x08 /* PWM Period Register */
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-#define MX1_PWMC_EN (1 << 4)
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+#define MX1_PWMC_EN (1 << 4)
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/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
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-#define MX3_PWMCR 0x00 /* PWM Control Register */
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-#define MX3_PWMSAR 0x0C /* PWM Sample Register */
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-#define MX3_PWMPR 0x10 /* PWM Period Register */
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-#define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
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-#define MX3_PWMCR_DOZEEN (1 << 24)
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-#define MX3_PWMCR_WAITEN (1 << 23)
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+#define MX3_PWMCR 0x00 /* PWM Control Register */
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+#define MX3_PWMSAR 0x0C /* PWM Sample Register */
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+#define MX3_PWMPR 0x10 /* PWM Period Register */
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+#define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
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+#define MX3_PWMCR_DOZEEN (1 << 24)
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+#define MX3_PWMCR_WAITEN (1 << 23)
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#define MX3_PWMCR_DBGEN (1 << 22)
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-#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
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-#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
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-#define MX3_PWMCR_EN (1 << 0)
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+#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
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+#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
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+#define MX3_PWMCR_EN (1 << 0)
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struct imx_chip {
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struct clk *clk_per;
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