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@@ -1288,9 +1288,7 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
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u32 tmp;
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int i;
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- tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL));
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- tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
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- WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL), tmp);
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+ WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
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gfx_v9_0_tiling_mode_table_init(adev);
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