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+#include <linux/highmem.h>
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+#include <linux/kdebug.h>
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+#include <linux/types.h>
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+#include <linux/notifier.h>
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+#include <linux/sched.h>
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+#include <linux/uprobes.h>
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+
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+#include <asm/branch.h>
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+#include <asm/cpu-features.h>
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+#include <asm/ptrace.h>
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+#include <asm/inst.h>
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+
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+static inline int insn_has_delay_slot(const union mips_instruction insn)
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+{
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+ switch (insn.i_format.opcode) {
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+ /*
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+ * jr and jalr are in r_format format.
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+ */
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+ case spec_op:
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+ switch (insn.r_format.func) {
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+ case jalr_op:
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+ case jr_op:
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+ return 1;
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+ }
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+ break;
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+
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+ /*
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+ * This group contains:
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+ * bltz_op, bgez_op, bltzl_op, bgezl_op,
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+ * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
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+ */
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+ case bcond_op:
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+ switch (insn.i_format.rt) {
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+ case bltz_op:
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+ case bltzl_op:
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+ case bgez_op:
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+ case bgezl_op:
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+ case bltzal_op:
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+ case bltzall_op:
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+ case bgezal_op:
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+ case bgezall_op:
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+ case bposge32_op:
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+ return 1;
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+ }
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+ break;
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+
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+ /*
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+ * These are unconditional and in j_format.
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+ */
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+ case jal_op:
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+ case j_op:
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+ case beq_op:
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+ case beql_op:
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+ case bne_op:
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+ case bnel_op:
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+ case blez_op: /* not really i_format */
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+ case blezl_op:
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+ case bgtz_op:
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+ case bgtzl_op:
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+ return 1;
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+
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+ /*
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+ * And now the FPA/cp1 branch instructions.
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+ */
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+ case cop1_op:
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+#ifdef CONFIG_CPU_CAVIUM_OCTEON
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+ case lwc2_op: /* This is bbit0 on Octeon */
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+ case ldc2_op: /* This is bbit032 on Octeon */
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+ case swc2_op: /* This is bbit1 on Octeon */
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+ case sdc2_op: /* This is bbit132 on Octeon */
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+#endif
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+ return 1;
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+ }
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+
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+ return 0;
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+}
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+
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+/**
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+ * arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
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+ * @mm: the probed address space.
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+ * @arch_uprobe: the probepoint information.
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+ * @addr: virtual address at which to install the probepoint
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+ * Return 0 on success or a -ve number on error.
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+ */
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+int arch_uprobe_analyze_insn(struct arch_uprobe *aup,
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+ struct mm_struct *mm, unsigned long addr)
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+{
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+ union mips_instruction inst;
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+
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+ /*
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+ * For the time being this also blocks attempts to use uprobes with
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+ * MIPS16 and microMIPS.
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+ */
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+ if (addr & 0x03)
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+ return -EINVAL;
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+
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+ inst.word = aup->insn[0];
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+ aup->ixol[0] = aup->insn[insn_has_delay_slot(inst)];
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+ aup->ixol[1] = UPROBE_BRK_UPROBE_XOL; /* NOP */
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+
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+ return 0;
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+}
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+
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+/**
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+ * is_trap_insn - check if the instruction is a trap variant
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+ * @insn: instruction to be checked.
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+ * Returns true if @insn is a trap variant.
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+ *
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+ * This definition overrides the weak definition in kernel/events/uprobes.c.
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+ * and is needed for the case where an architecture has multiple trap
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+ * instructions (like PowerPC or MIPS). We treat BREAK just like the more
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+ * modern conditional trap instructions.
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+ */
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+bool is_trap_insn(uprobe_opcode_t *insn)
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+{
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+ union mips_instruction inst;
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+
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+ inst.word = *insn;
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+
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+ switch (inst.i_format.opcode) {
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+ case spec_op:
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+ switch (inst.r_format.func) {
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+ case break_op:
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+ case teq_op:
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+ case tge_op:
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+ case tgeu_op:
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+ case tlt_op:
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+ case tltu_op:
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+ case tne_op:
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+ return 1;
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+ }
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+ break;
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+
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+ case bcond_op: /* Yes, really ... */
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+ switch (inst.u_format.rt) {
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+ case teqi_op:
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+ case tgei_op:
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+ case tgeiu_op:
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+ case tlti_op:
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+ case tltiu_op:
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+ case tnei_op:
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+ return 1;
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+ }
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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+#define UPROBE_TRAP_NR ULONG_MAX
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+
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+/*
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+ * arch_uprobe_pre_xol - prepare to execute out of line.
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+ * @auprobe: the probepoint information.
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+ * @regs: reflects the saved user state of current task.
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+ */
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+int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs)
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+{
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+ struct uprobe_task *utask = current->utask;
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+ union mips_instruction insn;
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+
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+ /*
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+ * Now find the EPC where to resume after the breakpoint has been
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+ * dealt with. This may require emulation of a branch.
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+ */
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+ aup->resume_epc = regs->cp0_epc + 4;
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+ if (insn_has_delay_slot((union mips_instruction) aup->insn[0])) {
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+ unsigned long epc;
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+
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+ epc = regs->cp0_epc;
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+ __compute_return_epc_for_insn(regs, insn);
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+ aup->resume_epc = regs->cp0_epc;
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+ }
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+
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+ utask->autask.saved_trap_nr = current->thread.trap_nr;
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+ current->thread.trap_nr = UPROBE_TRAP_NR;
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+ regs->cp0_epc = current->utask->xol_vaddr;
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+
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+ return 0;
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+}
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+
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+int arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs)
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+{
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+ struct uprobe_task *utask = current->utask;
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+
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+ current->thread.trap_nr = utask->autask.saved_trap_nr;
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+ regs->cp0_epc = aup->resume_epc;
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+
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+ return 0;
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+}
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+
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+/*
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+ * If xol insn itself traps and generates a signal(Say,
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+ * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
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+ * instruction jumps back to its own address. It is assumed that anything
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+ * like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
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+ *
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+ * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
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+ * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
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+ * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
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+ */
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+bool arch_uprobe_xol_was_trapped(struct task_struct *tsk)
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+{
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+ if (tsk->thread.trap_nr != UPROBE_TRAP_NR)
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+ return true;
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+
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+ return false;
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+}
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+
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+int arch_uprobe_exception_notify(struct notifier_block *self,
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+ unsigned long val, void *data)
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+{
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+ struct die_args *args = data;
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+ struct pt_regs *regs = args->regs;
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+
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+ /* regs == NULL is a kernel bug */
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+ if (WARN_ON(!regs))
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+ return NOTIFY_DONE;
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+
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+ /* We are only interested in userspace traps */
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+ if (!user_mode(regs))
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+ return NOTIFY_DONE;
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+
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+ switch (val) {
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+ case DIE_BREAK:
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+ if (uprobe_pre_sstep_notifier(regs))
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+ return NOTIFY_STOP;
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+ break;
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+ case DIE_UPROBE_XOL:
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+ if (uprobe_post_sstep_notifier(regs))
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+ return NOTIFY_STOP;
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+ default:
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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+/*
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+ * This function gets called when XOL instruction either gets trapped or
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+ * the thread has a fatal signal. Reset the instruction pointer to its
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+ * probed address for the potential restart or for post mortem analysis.
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+ */
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+void arch_uprobe_abort_xol(struct arch_uprobe *aup,
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+ struct pt_regs *regs)
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+{
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+ struct uprobe_task *utask = current->utask;
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+
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+ instruction_pointer_set(regs, utask->vaddr);
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+}
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+
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+unsigned long arch_uretprobe_hijack_return_addr(
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+ unsigned long trampoline_vaddr, struct pt_regs *regs)
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+{
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+ unsigned long ra;
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+
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+ ra = regs->regs[31];
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+
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+ /* Replace the return address with the trampoline address */
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+ regs->regs[31] = ra;
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+
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+ return ra;
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+}
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+
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+/**
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+ * set_swbp - store breakpoint at a given address.
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+ * @auprobe: arch specific probepoint information.
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+ * @mm: the probed process address space.
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+ * @vaddr: the virtual address to insert the opcode.
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+ *
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+ * For mm @mm, store the breakpoint instruction at @vaddr.
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+ * Return 0 (success) or a negative errno.
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+ *
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+ * This version overrides the weak version in kernel/events/uprobes.c.
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+ * It is required to handle MIPS16 and microMIPS.
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+ */
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+int __weak set_swbp(struct arch_uprobe *auprobe, struct mm_struct *mm,
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+ unsigned long vaddr)
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+{
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+ return uprobe_write_opcode(mm, vaddr, UPROBE_SWBP_INSN);
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+}
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+
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+/**
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+ * set_orig_insn - Restore the original instruction.
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+ * @mm: the probed process address space.
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+ * @auprobe: arch specific probepoint information.
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+ * @vaddr: the virtual address to insert the opcode.
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+ *
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+ * For mm @mm, restore the original opcode (opcode) at @vaddr.
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+ * Return 0 (success) or a negative errno.
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+ *
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+ * This overrides the weak version in kernel/events/uprobes.c.
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+ */
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+int set_orig_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
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+ unsigned long vaddr)
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+{
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+ return uprobe_write_opcode(mm, vaddr,
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+ *(uprobe_opcode_t *)&auprobe->orig_inst[0].word);
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+}
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+
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+void __weak arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
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+ void *src, unsigned long len)
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+{
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+ void *kaddr;
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+
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+ /* Initialize the slot */
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+ kaddr = kmap_atomic(page);
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+ memcpy(kaddr + (vaddr & ~PAGE_MASK), src, len);
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+ kunmap_atomic(kaddr);
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+
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+ /*
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+ * The MIPS version of flush_icache_range will operate safely on
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+ * user space addresses and more importantly, it doesn't require a
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+ * VMA argument.
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+ */
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+ flush_icache_range(vaddr, vaddr + len);
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+}
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+
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+/**
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+ * uprobe_get_swbp_addr - compute address of swbp given post-swbp regs
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+ * @regs: Reflects the saved state of the task after it has hit a breakpoint
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+ * instruction.
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+ * Return the address of the breakpoint instruction.
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+ *
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+ * This overrides the weak version in kernel/events/uprobes.c.
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+ */
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+unsigned long uprobe_get_swbp_addr(struct pt_regs *regs)
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+{
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+ return instruction_pointer(regs);
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+}
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+
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+/*
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+ * See if the instruction can be emulated.
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+ * Returns true if instruction was emulated, false otherwise.
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+ *
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+ * For now we always emulate so this function just returns 0.
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+ */
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+bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
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+{
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+ return 0;
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+}
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Ralf Baechle