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@@ -3257,14 +3257,15 @@ void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
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/**
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/**
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* i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
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* i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
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* @pf: board private structure
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* @pf: board private structure
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+ * @clearpba: true when all pending interrupt events should be cleared
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**/
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**/
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-void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
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+void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba)
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{
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{
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struct i40e_hw *hw = &pf->hw;
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struct i40e_hw *hw = &pf->hw;
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u32 val;
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u32 val;
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val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
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val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
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- I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
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+ (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) |
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(I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
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(I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
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wr32(hw, I40E_PFINT_DYN_CTL0, val);
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wr32(hw, I40E_PFINT_DYN_CTL0, val);
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@@ -3396,7 +3397,7 @@ static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
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for (i = 0; i < vsi->num_q_vectors; i++)
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for (i = 0; i < vsi->num_q_vectors; i++)
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i40e_irq_dynamic_enable(vsi, i);
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i40e_irq_dynamic_enable(vsi, i);
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} else {
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} else {
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- i40e_irq_dynamic_enable_icr0(pf);
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+ i40e_irq_dynamic_enable_icr0(pf, true);
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}
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}
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i40e_flush(&pf->hw);
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i40e_flush(&pf->hw);
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@@ -3542,7 +3543,7 @@ enable_intr:
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wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
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wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
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if (!test_bit(__I40E_DOWN, &pf->state)) {
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if (!test_bit(__I40E_DOWN, &pf->state)) {
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i40e_service_event_schedule(pf);
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i40e_service_event_schedule(pf);
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- i40e_irq_dynamic_enable_icr0(pf);
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+ i40e_irq_dynamic_enable_icr0(pf, false);
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}
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}
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return ret;
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return ret;
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@@ -7858,7 +7859,7 @@ static int i40e_setup_misc_vector(struct i40e_pf *pf)
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i40e_flush(hw);
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i40e_flush(hw);
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- i40e_irq_dynamic_enable_icr0(pf);
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+ i40e_irq_dynamic_enable_icr0(pf, true);
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return err;
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return err;
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}
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}
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