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@@ -81,6 +81,7 @@ static DEFINE_SPINLOCK(giu_lock);
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static unsigned long giu_flags;
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static void __iomem *giu_base;
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+static struct gpio_chip vr41xx_gpio_chip;
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#define giu_read(offset) readw(giu_base + (offset))
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#define giu_write(offset, value) writew((value), giu_base + (offset))
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@@ -135,12 +136,31 @@ static void unmask_giuint_low(struct irq_data *d)
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giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
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}
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+static unsigned int startup_giuint(struct irq_data *data)
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+{
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+ if (gpio_lock_as_irq(&vr41xx_gpio_chip, data->hwirq))
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+ dev_err(vr41xx_gpio_chip.dev,
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+ "unable to lock HW IRQ %lu for IRQ\n",
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+ data->hwirq);
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+ /* Satisfy the .enable semantics by unmasking the line */
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+ unmask_giuint_low(data);
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+ return 0;
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+}
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+
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+static void shutdown_giuint(struct irq_data *data)
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+{
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+ mask_giuint_low(data);
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+ gpio_unlock_as_irq(&vr41xx_gpio_chip, data->hwirq);
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+}
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+
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static struct irq_chip giuint_low_irq_chip = {
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.name = "GIUINTL",
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.irq_ack = ack_giuint_low,
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.irq_mask = mask_giuint_low,
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.irq_mask_ack = mask_ack_giuint_low,
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.irq_unmask = unmask_giuint_low,
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+ .irq_startup = startup_giuint,
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+ .irq_shutdown = shutdown_giuint,
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};
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static void ack_giuint_high(struct irq_data *d)
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