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@@ -1412,99 +1412,113 @@ static int stk807xpvr_frontend_attach1(struct dvb_usb_adapter *adap)
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/* STK8096GP */
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/* STK8096GP */
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static struct dibx000_agc_config dib8090_agc_config[2] = {
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static struct dibx000_agc_config dib8090_agc_config[2] = {
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{
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{
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- BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
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+ .band_caps = BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
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/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
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/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
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* P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
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* P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
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* P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
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* P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
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- (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
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+ .setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
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| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
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| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
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- 787,
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- 10,
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+ .inv_gain = 787,
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+ .time_stabiliz = 10,
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- 0,
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- 118,
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+ .alpha_level = 0,
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+ .thlock = 118,
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- 0,
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- 3530,
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- 1,
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- 5,
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+ .wbd_inv = 0,
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+ .wbd_ref = 3530,
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+ .wbd_sel = 1,
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+ .wbd_alpha = 5,
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- 65535,
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- 0,
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+ .agc1_max = 65535,
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+ .agc1_min = 0,
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- 65535,
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- 0,
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-
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- 0,
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- 32,
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- 114,
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- 143,
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- 144,
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- 114,
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- 227,
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- 116,
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- 117,
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-
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- 28,
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- 26,
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- 31,
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- 51,
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+ .agc2_max = 65535,
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+ .agc2_min = 0,
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- 0,
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+ .agc1_pt1 = 0,
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+ .agc1_pt2 = 32,
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+ .agc1_pt3 = 114,
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+ .agc1_slope1 = 143,
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+ .agc1_slope2 = 144,
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+ .agc2_pt1 = 114,
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+ .agc2_pt2 = 227,
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+ .agc2_slope1 = 116,
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+ .agc2_slope2 = 117,
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+
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+ .alpha_mant = 28,
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+ .alpha_exp = 26,
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+ .beta_mant = 31,
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+ .beta_exp = 51,
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+
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+ .perform_agc_softsplit = 0,
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},
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},
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{
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{
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- BAND_CBAND,
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+ .band_caps = BAND_CBAND,
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/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
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/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
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* P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
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* P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
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* P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
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* P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
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- (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
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+ .setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
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| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
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| (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
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- 787,
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- 10,
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+ .inv_gain = 787,
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+ .time_stabiliz = 10,
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- 0,
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- 118,
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+ .alpha_level = 0,
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+ .thlock = 118,
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- 0,
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- 3530,
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- 1,
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- 5,
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-
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- 0,
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- 0,
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-
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- 65535,
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- 0,
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+ .wbd_inv = 0,
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+ .wbd_ref = 3530,
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+ .wbd_sel = 1,
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+ .wbd_alpha = 5,
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- 0,
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- 32,
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- 114,
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- 143,
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- 144,
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- 114,
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- 227,
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- 116,
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- 117,
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+ .agc1_max = 0,
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+ .agc1_min = 0,
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- 28,
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- 26,
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- 31,
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- 51,
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+ .agc2_max = 65535,
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+ .agc2_min = 0,
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- 0,
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+ .agc1_pt1 = 0,
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+ .agc1_pt2 = 32,
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+ .agc1_pt3 = 114,
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+ .agc1_slope1 = 143,
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+ .agc1_slope2 = 144,
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+ .agc2_pt1 = 114,
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+ .agc2_pt2 = 227,
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+ .agc2_slope1 = 116,
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+ .agc2_slope2 = 117,
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+
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+ .alpha_mant = 28,
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+ .alpha_exp = 26,
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+ .beta_mant = 31,
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+ .beta_exp = 51,
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+
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+ .perform_agc_softsplit = 0,
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}
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}
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};
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};
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static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = {
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static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = {
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- 54000, 13500,
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- 1, 18, 3, 1, 0,
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- 0, 0, 1, 1, 2,
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- (3 << 14) | (1 << 12) | (599 << 0),
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- (0 << 25) | 0,
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- 20199727,
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- 12000000,
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+ .internal = 54000,
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+ .sampling = 13500,
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+
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+ .pll_prediv = 1,
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+ .pll_ratio = 18,
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+ .pll_range = 3,
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+ .pll_reset = 1,
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+ .pll_bypass = 0,
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+
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+ .enable_refdiv = 0,
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+ .bypclk_div = 0,
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+ .IO_CLK_en_core = 1,
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+ .ADClkSrc = 1,
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+ .modulo = 2,
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+
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+ .sad_cfg = (3 << 14) | (1 << 12) | (599 << 0),
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+
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+ .ifreq = (0 << 25) | 0,
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+ .timf = 20199727,
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+
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+ .xtal_hz = 12000000,
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};
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};
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static int dib8090_get_adc_power(struct dvb_frontend *fe)
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static int dib8090_get_adc_power(struct dvb_frontend *fe)
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