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@@ -22,7 +22,6 @@
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#include "regs-hdmi.h"
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#include <linux/kernel.h>
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-#include <linux/spinlock.h>
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#include <linux/wait.h>
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#include <linux/i2c.h>
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#include <linux/platform_device.h>
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@@ -33,8 +32,8 @@
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include <linux/io.h>
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-#include <linux/of.h>
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#include <linux/of_address.h>
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+#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/hdmi.h>
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#include <linux/component.h>
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@@ -48,7 +47,6 @@
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#include "exynos_mixer.h"
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#include <linux/gpio.h>
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-#include <media/s5p_hdmi.h>
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#define ctx_from_connector(c) container_of(c, struct hdmi_context, connector)
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@@ -88,109 +86,14 @@ struct hdmi_resources {
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int regul_count;
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};
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-struct hdmi_tg_regs {
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- u8 cmd[1];
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- u8 h_fsz[2];
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- u8 hact_st[2];
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- u8 hact_sz[2];
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- u8 v_fsz[2];
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- u8 vsync[2];
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- u8 vsync2[2];
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- u8 vact_st[2];
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- u8 vact_sz[2];
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- u8 field_chg[2];
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- u8 vact_st2[2];
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- u8 vact_st3[2];
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- u8 vact_st4[2];
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- u8 vsync_top_hdmi[2];
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- u8 vsync_bot_hdmi[2];
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- u8 field_top_hdmi[2];
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- u8 field_bot_hdmi[2];
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- u8 tg_3d[1];
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-};
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-
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-struct hdmi_v13_core_regs {
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- u8 h_blank[2];
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- u8 v_blank[3];
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- u8 h_v_line[3];
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- u8 vsync_pol[1];
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- u8 int_pro_mode[1];
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- u8 v_blank_f[3];
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- u8 h_sync_gen[3];
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- u8 v_sync_gen1[3];
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- u8 v_sync_gen2[3];
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- u8 v_sync_gen3[3];
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-};
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-
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-struct hdmi_v14_core_regs {
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- u8 h_blank[2];
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- u8 v2_blank[2];
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- u8 v1_blank[2];
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- u8 v_line[2];
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- u8 h_line[2];
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- u8 hsync_pol[1];
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- u8 vsync_pol[1];
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- u8 int_pro_mode[1];
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- u8 v_blank_f0[2];
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- u8 v_blank_f1[2];
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- u8 h_sync_start[2];
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- u8 h_sync_end[2];
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- u8 v_sync_line_bef_2[2];
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- u8 v_sync_line_bef_1[2];
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- u8 v_sync_line_aft_2[2];
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- u8 v_sync_line_aft_1[2];
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- u8 v_sync_line_aft_pxl_2[2];
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- u8 v_sync_line_aft_pxl_1[2];
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- u8 v_blank_f2[2]; /* for 3D mode */
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- u8 v_blank_f3[2]; /* for 3D mode */
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- u8 v_blank_f4[2]; /* for 3D mode */
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- u8 v_blank_f5[2]; /* for 3D mode */
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- u8 v_sync_line_aft_3[2];
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- u8 v_sync_line_aft_4[2];
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- u8 v_sync_line_aft_5[2];
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- u8 v_sync_line_aft_6[2];
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- u8 v_sync_line_aft_pxl_3[2];
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- u8 v_sync_line_aft_pxl_4[2];
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- u8 v_sync_line_aft_pxl_5[2];
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- u8 v_sync_line_aft_pxl_6[2];
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- u8 vact_space_1[2];
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- u8 vact_space_2[2];
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- u8 vact_space_3[2];
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- u8 vact_space_4[2];
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- u8 vact_space_5[2];
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- u8 vact_space_6[2];
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-};
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-
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-struct hdmi_v13_conf {
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- struct hdmi_v13_core_regs core;
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- struct hdmi_tg_regs tg;
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-};
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-
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-struct hdmi_v14_conf {
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- struct hdmi_v14_core_regs core;
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- struct hdmi_tg_regs tg;
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-};
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-
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-struct hdmi_conf_regs {
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- int pixel_clock;
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- int cea_video_id;
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- enum hdmi_picture_aspect aspect_ratio;
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- union {
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- struct hdmi_v13_conf v13_conf;
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- struct hdmi_v14_conf v14_conf;
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- } conf;
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-};
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-
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struct hdmi_context {
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- struct exynos_drm_display display;
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+ struct drm_encoder encoder;
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struct device *dev;
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struct drm_device *drm_dev;
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struct drm_connector connector;
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- struct drm_encoder *encoder;
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bool hpd;
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bool powered;
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bool dvi_mode;
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- struct mutex hdmi_mutex;
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void __iomem *regs;
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int irq;
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@@ -201,22 +104,20 @@ struct hdmi_context {
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/* current hdmiphy conf regs */
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struct drm_display_mode current_mode;
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- struct hdmi_conf_regs mode_conf;
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+ u8 cea_video_id;
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struct hdmi_resources res;
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+ const struct hdmi_driver_data *drv_data;
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int hpd_gpio;
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void __iomem *regs_hdmiphy;
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- const struct hdmiphy_config *phy_confs;
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- unsigned int phy_conf_count;
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struct regmap *pmureg;
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- enum hdmi_type type;
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};
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-static inline struct hdmi_context *display_to_hdmi(struct exynos_drm_display *d)
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+static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
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{
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- return container_of(d, struct hdmi_context, display);
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+ return container_of(e, struct hdmi_context, encoder);
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}
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struct hdmiphy_config {
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@@ -624,6 +525,16 @@ static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
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writeb(value, hdata->regs + reg_id);
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}
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+static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id,
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+ int bytes, u32 val)
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+{
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+ while (--bytes >= 0) {
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+ writeb(val & 0xff, hdata->regs + reg_id);
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+ val >>= 8;
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+ reg_id += 4;
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+ }
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+}
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+
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static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
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u32 reg_id, u32 value, u32 mask)
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{
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@@ -930,7 +841,7 @@ static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
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static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
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{
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- if (hdata->type == HDMI_TYPE13)
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+ if (hdata->drv_data->type == HDMI_TYPE13)
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hdmi_v13_regs_dump(hdata, prefix);
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else
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hdmi_v14_regs_dump(hdata, prefix);
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@@ -957,7 +868,7 @@ static void hdmi_reg_infoframe(struct hdmi_context *hdata,
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u32 hdr_sum;
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u8 chksum;
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u32 mod;
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- u32 vic;
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+ u8 ar;
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mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
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if (hdata->dvi_mode) {
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@@ -988,27 +899,22 @@ static void hdmi_reg_infoframe(struct hdmi_context *hdata,
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* Set the aspect ratio as per the mode, mentioned in
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* Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
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*/
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- switch (hdata->mode_conf.aspect_ratio) {
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+ ar = hdata->current_mode.picture_aspect_ratio;
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+ switch (ar) {
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case HDMI_PICTURE_ASPECT_4_3:
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- hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
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- hdata->mode_conf.aspect_ratio |
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- AVI_4_3_CENTER_RATIO);
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+ ar |= AVI_4_3_CENTER_RATIO;
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break;
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case HDMI_PICTURE_ASPECT_16_9:
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- hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
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- hdata->mode_conf.aspect_ratio |
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- AVI_16_9_CENTER_RATIO);
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+ ar |= AVI_16_9_CENTER_RATIO;
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break;
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case HDMI_PICTURE_ASPECT_NONE:
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default:
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- hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
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- hdata->mode_conf.aspect_ratio |
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- AVI_SAME_AS_PIC_ASPECT_RATIO);
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+ ar |= AVI_SAME_AS_PIC_ASPECT_RATIO;
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break;
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}
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+ hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), ar);
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- vic = hdata->mode_conf.cea_video_id;
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- hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
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+ hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->cea_video_id);
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chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
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infoframe->any.length, hdr_sum);
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@@ -1038,10 +944,10 @@ static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
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{
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struct hdmi_context *hdata = ctx_from_connector(connector);
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- hdata->hpd = gpio_get_value(hdata->hpd_gpio);
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+ if (gpio_get_value(hdata->hpd_gpio))
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+ return connector_status_connected;
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- return hdata->hpd ? connector_status_connected :
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- connector_status_disconnected;
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+ return connector_status_disconnected;
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}
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static void hdmi_connector_destroy(struct drm_connector *connector)
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@@ -1091,8 +997,8 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
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{
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int i;
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- for (i = 0; i < hdata->phy_conf_count; i++)
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- if (hdata->phy_confs[i].pixel_clock == pixel_clock)
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+ for (i = 0; i < hdata->drv_data->phy_conf_count; i++)
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+ if (hdata->drv_data->phy_confs[i].pixel_clock == pixel_clock)
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return i;
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DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
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@@ -1125,7 +1031,7 @@ static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector)
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{
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struct hdmi_context *hdata = ctx_from_connector(connector);
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- return hdata->encoder;
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+ return &hdata->encoder;
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}
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static struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
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@@ -1134,14 +1040,12 @@ static struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
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.best_encoder = hdmi_best_encoder,
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};
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-static int hdmi_create_connector(struct exynos_drm_display *display,
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- struct drm_encoder *encoder)
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+static int hdmi_create_connector(struct drm_encoder *encoder)
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{
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- struct hdmi_context *hdata = display_to_hdmi(display);
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+ struct hdmi_context *hdata = encoder_to_hdmi(encoder);
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struct drm_connector *connector = &hdata->connector;
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int ret;
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- hdata->encoder = encoder;
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connector->interlace_allowed = true;
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connector->polled = DRM_CONNECTOR_POLL_HPD;
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@@ -1159,23 +1063,30 @@ static int hdmi_create_connector(struct exynos_drm_display *display,
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return 0;
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}
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-static void hdmi_mode_fixup(struct exynos_drm_display *display,
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- struct drm_connector *connector,
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- const struct drm_display_mode *mode,
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- struct drm_display_mode *adjusted_mode)
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+static bool hdmi_mode_fixup(struct drm_encoder *encoder,
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+ const struct drm_display_mode *mode,
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+ struct drm_display_mode *adjusted_mode)
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{
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+ struct drm_device *dev = encoder->dev;
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+ struct drm_connector *connector;
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struct drm_display_mode *m;
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int mode_ok;
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- DRM_DEBUG_KMS("%s\n", __FILE__);
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-
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drm_mode_set_crtcinfo(adjusted_mode, 0);
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+ list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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+ if (connector->encoder == encoder)
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+ break;
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+ }
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+
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+ if (connector->encoder != encoder)
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+ return true;
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+
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mode_ok = hdmi_mode_valid(connector, adjusted_mode);
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/* just return if user desired mode exists. */
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if (mode_ok == MODE_OK)
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- return;
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+ return true;
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/*
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* otherwise, find the most suitable mode among modes and change it
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@@ -1195,6 +1106,8 @@ static void hdmi_mode_fixup(struct exynos_drm_display *display,
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break;
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}
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}
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+
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+ return true;
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}
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static void hdmi_set_acr(u32 freq, u8 *acr)
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@@ -1257,7 +1170,7 @@ static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
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hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
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hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
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- if (hdata->type == HDMI_TYPE13)
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+ if (hdata->drv_data->type == HDMI_TYPE13)
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hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
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else
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hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
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@@ -1391,7 +1304,7 @@ static void hdmi_conf_init(struct hdmi_context *hdata)
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HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
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}
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- if (hdata->type == HDMI_TYPE13) {
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+ if (hdata->drv_data->type == HDMI_TYPE13) {
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/* choose bluescreen (fecal) color */
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hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
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hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
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@@ -1424,66 +1337,94 @@ static void hdmi_conf_init(struct hdmi_context *hdata)
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static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
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{
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- const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
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- const struct hdmi_v13_core_regs *core =
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- &hdata->mode_conf.conf.v13_conf.core;
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+ struct drm_display_mode *m = &hdata->current_mode;
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+ unsigned int val;
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int tries;
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- /* setting core registers */
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- hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
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- hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
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- hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
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- hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
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- hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
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- hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
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- hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
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- hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
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- hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
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- hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3,
|
|
|
+ (m->htotal << 12) | m->vtotal);
|
|
|
+
|
|
|
+ val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
|
|
|
+ hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val);
|
|
|
+
|
|
|
+ val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
|
|
|
+ hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val);
|
|
|
+
|
|
|
+ val = (m->hsync_start - m->hdisplay - 2);
|
|
|
+ val |= ((m->hsync_end - m->hdisplay - 2) << 10);
|
|
|
+ val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Quirk requirement for exynos HDMI IP design,
|
|
|
+ * 2 pixels less than the actual calculation for hsync_start
|
|
|
+ * and end.
|
|
|
+ */
|
|
|
+
|
|
|
+ /* Following values & calculations differ for different type of modes */
|
|
|
+ if (m->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
|
+ /* Interlaced Mode */
|
|
|
+ val = ((m->vsync_end - m->vdisplay) / 2);
|
|
|
+ val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
|
|
|
+
|
|
|
+ val = m->vtotal / 2;
|
|
|
+ val |= ((m->vtotal - m->vdisplay) / 2) << 11;
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
|
|
|
+
|
|
|
+ val = (m->vtotal +
|
|
|
+ ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
|
|
|
+ val |= m->vtotal << 11;
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val);
|
|
|
+
|
|
|
+ val = ((m->vtotal / 2) + 7);
|
|
|
+ val |= ((m->vtotal / 2) + 2) << 12;
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val);
|
|
|
+
|
|
|
+ val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
|
|
|
+ val |= ((m->htotal / 2) +
|
|
|
+ (m->hsync_start - m->hdisplay)) << 12;
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val);
|
|
|
+
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
|
|
|
+ (m->vtotal - m->vdisplay) / 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
|
|
|
+
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x249);
|
|
|
+ } else {
|
|
|
+ /* Progressive Mode */
|
|
|
+
|
|
|
+ val = m->vtotal;
|
|
|
+ val |= (m->vtotal - m->vdisplay) << 11;
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
|
|
|
+
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, 0);
|
|
|
+
|
|
|
+ val = (m->vsync_end - m->vdisplay);
|
|
|
+ val |= ((m->vsync_start - m->vdisplay) << 12);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
|
|
|
+
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, 0x1001);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, 0x1001);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
|
|
|
+ m->vtotal - m->vdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x248);
|
|
|
+ }
|
|
|
+
|
|
|
/* Timing generator registers */
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VSYNC_L, 2, 0x1);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2, 0x233);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_FIELD_CHG_L, 2, 0x233);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, 2, 0x1);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2, 0x233);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_FIELD_TOP_HDMI_L, 2, 0x1);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2, 0x233);
|
|
|
|
|
|
/* waiting for HDMIPHY's PLL to get to steady state */
|
|
|
for (tries = 100; tries; --tries) {
|
|
@@ -1508,144 +1449,119 @@ static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
|
|
|
|
|
|
static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
|
|
|
{
|
|
|
- const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
|
|
|
- const struct hdmi_v14_core_regs *core =
|
|
|
- &hdata->mode_conf.conf.v14_conf.core;
|
|
|
+ struct drm_display_mode *m = &hdata->current_mode;
|
|
|
int tries;
|
|
|
|
|
|
- /* setting core registers */
|
|
|
- hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
|
|
|
- core->v_sync_line_bef_2[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
|
|
|
- core->v_sync_line_bef_2[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
|
|
|
- core->v_sync_line_bef_1[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
|
|
|
- core->v_sync_line_bef_1[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
|
|
|
- core->v_sync_line_aft_2[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
|
|
|
- core->v_sync_line_aft_2[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
|
|
|
- core->v_sync_line_aft_1[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
|
|
|
- core->v_sync_line_aft_1[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
|
|
|
- core->v_sync_line_aft_pxl_2[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
|
|
|
- core->v_sync_line_aft_pxl_2[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
|
|
|
- core->v_sync_line_aft_pxl_1[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
|
|
|
- core->v_sync_line_aft_pxl_1[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
|
|
|
- core->v_sync_line_aft_3[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
|
|
|
- core->v_sync_line_aft_3[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
|
|
|
- core->v_sync_line_aft_4[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
|
|
|
- core->v_sync_line_aft_4[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
|
|
|
- core->v_sync_line_aft_5[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
|
|
|
- core->v_sync_line_aft_5[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
|
|
|
- core->v_sync_line_aft_6[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
|
|
|
- core->v_sync_line_aft_6[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
|
|
|
- core->v_sync_line_aft_pxl_3[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
|
|
|
- core->v_sync_line_aft_pxl_3[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
|
|
|
- core->v_sync_line_aft_pxl_4[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
|
|
|
- core->v_sync_line_aft_pxl_4[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
|
|
|
- core->v_sync_line_aft_pxl_5[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
|
|
|
- core->v_sync_line_aft_pxl_5[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
|
|
|
- core->v_sync_line_aft_pxl_6[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
|
|
|
- core->v_sync_line_aft_pxl_6[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_HSYNC_POL, 1,
|
|
|
+ (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1,
|
|
|
+ (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1,
|
|
|
+ (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Quirk requirement for exynos 5 HDMI IP design,
|
|
|
+ * 2 pixels less than the actual calculation for hsync_start
|
|
|
+ * and end.
|
|
|
+ */
|
|
|
+
|
|
|
+ /* Following values & calculations differ for different type of modes */
|
|
|
+ if (m->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
|
+ /* Interlaced Mode */
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
|
|
|
+ (m->vsync_end - m->vdisplay) / 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
|
|
|
+ (m->vsync_start - m->vdisplay) / 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal / 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
|
|
|
+ (m->vtotal - m->vdisplay) / 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2,
|
|
|
+ m->vtotal - m->vdisplay / 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, m->vtotal);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2,
|
|
|
+ (m->vtotal / 2) + 7);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2,
|
|
|
+ (m->vtotal / 2) + 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2,
|
|
|
+ (m->htotal / 2) + (m->hsync_start - m->hdisplay));
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2,
|
|
|
+ (m->htotal / 2) + (m->hsync_start - m->hdisplay));
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
|
|
|
+ (m->vtotal - m->vdisplay) / 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2,
|
|
|
+ m->vtotal - m->vdisplay / 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2,
|
|
|
+ (m->vtotal / 2) + 1);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2,
|
|
|
+ (m->vtotal / 2) + 1);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2,
|
|
|
+ (m->vtotal / 2) + 1);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x0);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x0);
|
|
|
+ } else {
|
|
|
+ /* Progressive Mode */
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
|
|
|
+ m->vsync_end - m->vdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
|
|
|
+ m->vsync_start - m->vdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
|
|
|
+ m->vtotal - m->vdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
|
|
|
+ m->vtotal - m->vdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x248);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x47b);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x6ae);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2, 0x233);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2, 0x233);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2, 0x233);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Following values & calculations are same irrespective of mode type */
|
|
|
+ hdmi_reg_writev(hdata, HDMI_H_SYNC_START_0, 2,
|
|
|
+ m->hsync_start - m->hdisplay - 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_H_SYNC_END_0, 2,
|
|
|
+ m->hsync_end - m->hdisplay - 2);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_VACT_SPACE_1_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_VACT_SPACE_2_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_VACT_SPACE_3_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_VACT_SPACE_4_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_VACT_SPACE_5_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_VACT_SPACE_6_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_BLANK_F2_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_BLANK_F3_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_BLANK_F4_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_BLANK_F5_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 2, 0xffff);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff);
|
|
|
|
|
|
/* Timing generator registers */
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
|
|
|
- hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VSYNC_L, 2, 0x1);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_FIELD_CHG_L, 2, 0x233);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, 2, 0x1);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_FIELD_TOP_HDMI_L, 2, 0x1);
|
|
|
+ hdmi_reg_writev(hdata, HDMI_TG_3D, 1, 0x0);
|
|
|
|
|
|
/* waiting for HDMIPHY's PLL to get to steady state */
|
|
|
for (tries = 100; tries; --tries) {
|
|
@@ -1670,7 +1586,7 @@ static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
|
|
|
|
|
|
static void hdmi_mode_apply(struct hdmi_context *hdata)
|
|
|
{
|
|
|
- if (hdata->type == HDMI_TYPE13)
|
|
|
+ if (hdata->drv_data->type == HDMI_TYPE13)
|
|
|
hdmi_v13_mode_apply(hdata);
|
|
|
else
|
|
|
hdmi_v14_mode_apply(hdata);
|
|
@@ -1688,7 +1604,7 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata)
|
|
|
hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
|
|
|
HDMI_PHY_ENABLE_MODE_SET);
|
|
|
|
|
|
- if (hdata->type == HDMI_TYPE13)
|
|
|
+ if (hdata->drv_data->type == HDMI_TYPE13)
|
|
|
reg = HDMI_V13_PHY_RSTOUT;
|
|
|
else
|
|
|
reg = HDMI_PHY_RSTOUT;
|
|
@@ -1702,7 +1618,7 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata)
|
|
|
|
|
|
static void hdmiphy_poweron(struct hdmi_context *hdata)
|
|
|
{
|
|
|
- if (hdata->type != HDMI_TYPE14)
|
|
|
+ if (hdata->drv_data->type != HDMI_TYPE14)
|
|
|
return;
|
|
|
|
|
|
DRM_DEBUG_KMS("\n");
|
|
@@ -1722,7 +1638,7 @@ static void hdmiphy_poweron(struct hdmi_context *hdata)
|
|
|
|
|
|
static void hdmiphy_poweroff(struct hdmi_context *hdata)
|
|
|
{
|
|
|
- if (hdata->type != HDMI_TYPE14)
|
|
|
+ if (hdata->drv_data->type != HDMI_TYPE14)
|
|
|
return;
|
|
|
|
|
|
DRM_DEBUG_KMS("\n");
|
|
@@ -1748,13 +1664,14 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
|
|
|
int i;
|
|
|
|
|
|
/* pixel clock */
|
|
|
- i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock);
|
|
|
+ i = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000);
|
|
|
if (i < 0) {
|
|
|
DRM_ERROR("failed to find hdmiphy conf\n");
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
- ret = hdmiphy_reg_write_buf(hdata, 0, hdata->phy_confs[i].conf, 32);
|
|
|
+ ret = hdmiphy_reg_write_buf(hdata, 0,
|
|
|
+ hdata->drv_data->phy_confs[i].conf, 32);
|
|
|
if (ret) {
|
|
|
DRM_ERROR("failed to configure hdmiphy\n");
|
|
|
return;
|
|
@@ -1776,10 +1693,8 @@ static void hdmi_conf_apply(struct hdmi_context *hdata)
|
|
|
hdmiphy_conf_reset(hdata);
|
|
|
hdmiphy_conf_apply(hdata);
|
|
|
|
|
|
- mutex_lock(&hdata->hdmi_mutex);
|
|
|
hdmi_start(hdata, false);
|
|
|
hdmi_conf_init(hdata);
|
|
|
- mutex_unlock(&hdata->hdmi_mutex);
|
|
|
|
|
|
hdmi_audio_init(hdata);
|
|
|
|
|
@@ -1790,271 +1705,32 @@ static void hdmi_conf_apply(struct hdmi_context *hdata)
|
|
|
hdmi_regs_dump(hdata, "start");
|
|
|
}
|
|
|
|
|
|
-static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
|
|
|
-{
|
|
|
- int i;
|
|
|
- BUG_ON(num_bytes > 4);
|
|
|
- for (i = 0; i < num_bytes; i++)
|
|
|
- reg_pair[i] = (value >> (8 * i)) & 0xff;
|
|
|
-}
|
|
|
-
|
|
|
-static void hdmi_v13_mode_set(struct hdmi_context *hdata,
|
|
|
- struct drm_display_mode *m)
|
|
|
+static void hdmi_mode_set(struct drm_encoder *encoder,
|
|
|
+ struct drm_display_mode *mode,
|
|
|
+ struct drm_display_mode *adjusted_mode)
|
|
|
{
|
|
|
- struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core;
|
|
|
- struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
|
|
|
- unsigned int val;
|
|
|
-
|
|
|
- hdata->mode_conf.cea_video_id =
|
|
|
- drm_match_cea_mode((struct drm_display_mode *)m);
|
|
|
- hdata->mode_conf.pixel_clock = m->clock * 1000;
|
|
|
- hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
|
|
|
-
|
|
|
- hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
|
|
|
- hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
|
|
|
-
|
|
|
- val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
|
|
|
- hdmi_set_reg(core->vsync_pol, 1, val);
|
|
|
-
|
|
|
- val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
|
|
|
- hdmi_set_reg(core->int_pro_mode, 1, val);
|
|
|
-
|
|
|
- val = (m->hsync_start - m->hdisplay - 2);
|
|
|
- val |= ((m->hsync_end - m->hdisplay - 2) << 10);
|
|
|
- val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
|
|
|
- hdmi_set_reg(core->h_sync_gen, 3, val);
|
|
|
-
|
|
|
- /*
|
|
|
- * Quirk requirement for exynos HDMI IP design,
|
|
|
- * 2 pixels less than the actual calculation for hsync_start
|
|
|
- * and end.
|
|
|
- */
|
|
|
-
|
|
|
- /* Following values & calculations differ for different type of modes */
|
|
|
- if (m->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
|
- /* Interlaced Mode */
|
|
|
- val = ((m->vsync_end - m->vdisplay) / 2);
|
|
|
- val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
|
|
|
- hdmi_set_reg(core->v_sync_gen1, 3, val);
|
|
|
-
|
|
|
- val = m->vtotal / 2;
|
|
|
- val |= ((m->vtotal - m->vdisplay) / 2) << 11;
|
|
|
- hdmi_set_reg(core->v_blank, 3, val);
|
|
|
-
|
|
|
- val = (m->vtotal +
|
|
|
- ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
|
|
|
- val |= m->vtotal << 11;
|
|
|
- hdmi_set_reg(core->v_blank_f, 3, val);
|
|
|
-
|
|
|
- val = ((m->vtotal / 2) + 7);
|
|
|
- val |= ((m->vtotal / 2) + 2) << 12;
|
|
|
- hdmi_set_reg(core->v_sync_gen2, 3, val);
|
|
|
-
|
|
|
- val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
|
|
|
- val |= ((m->htotal / 2) +
|
|
|
- (m->hsync_start - m->hdisplay)) << 12;
|
|
|
- hdmi_set_reg(core->v_sync_gen3, 3, val);
|
|
|
-
|
|
|
- hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
|
|
|
- hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
|
|
|
-
|
|
|
- hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
|
|
|
- } else {
|
|
|
- /* Progressive Mode */
|
|
|
-
|
|
|
- val = m->vtotal;
|
|
|
- val |= (m->vtotal - m->vdisplay) << 11;
|
|
|
- hdmi_set_reg(core->v_blank, 3, val);
|
|
|
-
|
|
|
- hdmi_set_reg(core->v_blank_f, 3, 0);
|
|
|
-
|
|
|
- val = (m->vsync_end - m->vdisplay);
|
|
|
- val |= ((m->vsync_start - m->vdisplay) << 12);
|
|
|
- hdmi_set_reg(core->v_sync_gen1, 3, val);
|
|
|
-
|
|
|
- hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value */
|
|
|
- hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value */
|
|
|
- hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
|
|
|
- hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
|
|
|
- hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
|
|
|
- }
|
|
|
-
|
|
|
- /* Timing generator registers */
|
|
|
- hdmi_set_reg(tg->cmd, 1, 0x0);
|
|
|
- hdmi_set_reg(tg->h_fsz, 2, m->htotal);
|
|
|
- hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
|
|
|
- hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
|
|
|
- hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
|
|
|
- hdmi_set_reg(tg->vsync, 2, 0x1);
|
|
|
- hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
|
|
|
- hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
|
|
|
- hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
|
|
|
- hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
|
|
|
- hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
|
|
|
- hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
|
|
|
- hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */
|
|
|
-}
|
|
|
-
|
|
|
-static void hdmi_v14_mode_set(struct hdmi_context *hdata,
|
|
|
- struct drm_display_mode *m)
|
|
|
-{
|
|
|
- struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
|
|
|
- struct hdmi_v14_core_regs *core =
|
|
|
- &hdata->mode_conf.conf.v14_conf.core;
|
|
|
-
|
|
|
- hdata->mode_conf.cea_video_id =
|
|
|
- drm_match_cea_mode((struct drm_display_mode *)m);
|
|
|
- hdata->mode_conf.pixel_clock = m->clock * 1000;
|
|
|
- hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
|
|
|
-
|
|
|
- hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
|
|
|
- hdmi_set_reg(core->v_line, 2, m->vtotal);
|
|
|
- hdmi_set_reg(core->h_line, 2, m->htotal);
|
|
|
- hdmi_set_reg(core->hsync_pol, 1,
|
|
|
- (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
|
|
|
- hdmi_set_reg(core->vsync_pol, 1,
|
|
|
- (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
|
|
|
- hdmi_set_reg(core->int_pro_mode, 1,
|
|
|
- (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
|
|
|
-
|
|
|
- /*
|
|
|
- * Quirk requirement for exynos 5 HDMI IP design,
|
|
|
- * 2 pixels less than the actual calculation for hsync_start
|
|
|
- * and end.
|
|
|
- */
|
|
|
-
|
|
|
- /* Following values & calculations differ for different type of modes */
|
|
|
- if (m->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
|
- /* Interlaced Mode */
|
|
|
- hdmi_set_reg(core->v_sync_line_bef_2, 2,
|
|
|
- (m->vsync_end - m->vdisplay) / 2);
|
|
|
- hdmi_set_reg(core->v_sync_line_bef_1, 2,
|
|
|
- (m->vsync_start - m->vdisplay) / 2);
|
|
|
- hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
|
|
|
- hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
|
|
|
- hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2);
|
|
|
- hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
|
|
|
- (m->htotal / 2) + (m->hsync_start - m->hdisplay));
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
|
|
|
- (m->htotal / 2) + (m->hsync_start - m->hdisplay));
|
|
|
- hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
|
|
|
- hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
|
|
|
- hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2);
|
|
|
- hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1);
|
|
|
- hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1);
|
|
|
- hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1);
|
|
|
- hdmi_set_reg(tg->vact_st3, 2, 0x0);
|
|
|
- hdmi_set_reg(tg->vact_st4, 2, 0x0);
|
|
|
- } else {
|
|
|
- /* Progressive Mode */
|
|
|
- hdmi_set_reg(core->v_sync_line_bef_2, 2,
|
|
|
- m->vsync_end - m->vdisplay);
|
|
|
- hdmi_set_reg(core->v_sync_line_bef_1, 2,
|
|
|
- m->vsync_start - m->vdisplay);
|
|
|
- hdmi_set_reg(core->v2_blank, 2, m->vtotal);
|
|
|
- hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
|
|
|
- hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
|
|
|
- hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
|
|
|
- hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
|
|
|
- hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
|
|
|
- hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
|
|
|
- hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
|
|
|
- hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
|
|
|
- hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
|
|
|
- hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
|
|
|
- }
|
|
|
-
|
|
|
- /* Following values & calculations are same irrespective of mode type */
|
|
|
- hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
|
|
|
- hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
|
|
|
- hdmi_set_reg(core->vact_space_1, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->vact_space_2, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->vact_space_3, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->vact_space_4, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->vact_space_5, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->vact_space_6, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
|
|
|
- hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
|
|
|
-
|
|
|
- /* Timing generator registers */
|
|
|
- hdmi_set_reg(tg->cmd, 1, 0x0);
|
|
|
- hdmi_set_reg(tg->h_fsz, 2, m->htotal);
|
|
|
- hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
|
|
|
- hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
|
|
|
- hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
|
|
|
- hdmi_set_reg(tg->vsync, 2, 0x1);
|
|
|
- hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
|
|
|
- hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
|
|
|
- hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
|
|
|
- hdmi_set_reg(tg->tg_3d, 1, 0x0);
|
|
|
-}
|
|
|
-
|
|
|
-static void hdmi_mode_set(struct exynos_drm_display *display,
|
|
|
- struct drm_display_mode *mode)
|
|
|
-{
|
|
|
- struct hdmi_context *hdata = display_to_hdmi(display);
|
|
|
- struct drm_display_mode *m = mode;
|
|
|
+ struct hdmi_context *hdata = encoder_to_hdmi(encoder);
|
|
|
+ struct drm_display_mode *m = adjusted_mode;
|
|
|
|
|
|
DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
|
|
|
m->hdisplay, m->vdisplay,
|
|
|
m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
|
|
|
"INTERLACED" : "PROGRESSIVE");
|
|
|
|
|
|
- /* preserve mode information for later use. */
|
|
|
- drm_mode_copy(&hdata->current_mode, mode);
|
|
|
-
|
|
|
- if (hdata->type == HDMI_TYPE13)
|
|
|
- hdmi_v13_mode_set(hdata, mode);
|
|
|
- else
|
|
|
- hdmi_v14_mode_set(hdata, mode);
|
|
|
-}
|
|
|
-
|
|
|
-static void hdmi_commit(struct exynos_drm_display *display)
|
|
|
-{
|
|
|
- struct hdmi_context *hdata = display_to_hdmi(display);
|
|
|
-
|
|
|
- mutex_lock(&hdata->hdmi_mutex);
|
|
|
- if (!hdata->powered) {
|
|
|
- mutex_unlock(&hdata->hdmi_mutex);
|
|
|
- return;
|
|
|
- }
|
|
|
- mutex_unlock(&hdata->hdmi_mutex);
|
|
|
-
|
|
|
- hdmi_conf_apply(hdata);
|
|
|
+ drm_mode_copy(&hdata->current_mode, m);
|
|
|
+ hdata->cea_video_id = drm_match_cea_mode(mode);
|
|
|
}
|
|
|
|
|
|
-static void hdmi_poweron(struct hdmi_context *hdata)
|
|
|
+static void hdmi_enable(struct drm_encoder *encoder)
|
|
|
{
|
|
|
+ struct hdmi_context *hdata = encoder_to_hdmi(encoder);
|
|
|
struct hdmi_resources *res = &hdata->res;
|
|
|
|
|
|
- mutex_lock(&hdata->hdmi_mutex);
|
|
|
- if (hdata->powered) {
|
|
|
- mutex_unlock(&hdata->hdmi_mutex);
|
|
|
+ if (hdata->powered)
|
|
|
return;
|
|
|
- }
|
|
|
|
|
|
hdata->powered = true;
|
|
|
|
|
|
- mutex_unlock(&hdata->hdmi_mutex);
|
|
|
-
|
|
|
pm_runtime_get_sync(hdata->dev);
|
|
|
|
|
|
if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
|
|
@@ -2068,17 +1744,32 @@ static void hdmi_poweron(struct hdmi_context *hdata)
|
|
|
clk_prepare_enable(res->sclk_hdmi);
|
|
|
|
|
|
hdmiphy_poweron(hdata);
|
|
|
- hdmi_commit(&hdata->display);
|
|
|
+ hdmi_conf_apply(hdata);
|
|
|
}
|
|
|
|
|
|
-static void hdmi_poweroff(struct hdmi_context *hdata)
|
|
|
+static void hdmi_disable(struct drm_encoder *encoder)
|
|
|
{
|
|
|
+ struct hdmi_context *hdata = encoder_to_hdmi(encoder);
|
|
|
struct hdmi_resources *res = &hdata->res;
|
|
|
+ struct drm_crtc *crtc = encoder->crtc;
|
|
|
+ const struct drm_crtc_helper_funcs *funcs = NULL;
|
|
|
|
|
|
- mutex_lock(&hdata->hdmi_mutex);
|
|
|
if (!hdata->powered)
|
|
|
- goto out;
|
|
|
- mutex_unlock(&hdata->hdmi_mutex);
|
|
|
+ return;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * The SFRs of VP and Mixer are updated by Vertical Sync of
|
|
|
+ * Timing generator which is a part of HDMI so the sequence
|
|
|
+ * to disable TV Subsystem should be as following,
|
|
|
+ * VP -> Mixer -> HDMI
|
|
|
+ *
|
|
|
+ * Below codes will try to disable Mixer and VP(if used)
|
|
|
+ * prior to disabling HDMI.
|
|
|
+ */
|
|
|
+ if (crtc)
|
|
|
+ funcs = crtc->helper_private;
|
|
|
+ if (funcs && funcs->disable)
|
|
|
+ (*funcs->disable)(crtc);
|
|
|
|
|
|
/* HDMI System Disable */
|
|
|
hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
|
|
@@ -2098,57 +1789,18 @@ static void hdmi_poweroff(struct hdmi_context *hdata)
|
|
|
|
|
|
pm_runtime_put_sync(hdata->dev);
|
|
|
|
|
|
- mutex_lock(&hdata->hdmi_mutex);
|
|
|
hdata->powered = false;
|
|
|
-
|
|
|
-out:
|
|
|
- mutex_unlock(&hdata->hdmi_mutex);
|
|
|
-}
|
|
|
-
|
|
|
-static void hdmi_dpms(struct exynos_drm_display *display, int mode)
|
|
|
-{
|
|
|
- struct hdmi_context *hdata = display_to_hdmi(display);
|
|
|
- struct drm_encoder *encoder = hdata->encoder;
|
|
|
- struct drm_crtc *crtc = encoder->crtc;
|
|
|
- const struct drm_crtc_helper_funcs *funcs = NULL;
|
|
|
-
|
|
|
- DRM_DEBUG_KMS("mode %d\n", mode);
|
|
|
-
|
|
|
- switch (mode) {
|
|
|
- case DRM_MODE_DPMS_ON:
|
|
|
- hdmi_poweron(hdata);
|
|
|
- break;
|
|
|
- case DRM_MODE_DPMS_STANDBY:
|
|
|
- case DRM_MODE_DPMS_SUSPEND:
|
|
|
- case DRM_MODE_DPMS_OFF:
|
|
|
- /*
|
|
|
- * The SFRs of VP and Mixer are updated by Vertical Sync of
|
|
|
- * Timing generator which is a part of HDMI so the sequence
|
|
|
- * to disable TV Subsystem should be as following,
|
|
|
- * VP -> Mixer -> HDMI
|
|
|
- *
|
|
|
- * Below codes will try to disable Mixer and VP(if used)
|
|
|
- * prior to disabling HDMI.
|
|
|
- */
|
|
|
- if (crtc)
|
|
|
- funcs = crtc->helper_private;
|
|
|
- if (funcs && funcs->disable)
|
|
|
- (*funcs->disable)(crtc);
|
|
|
-
|
|
|
- hdmi_poweroff(hdata);
|
|
|
- break;
|
|
|
- default:
|
|
|
- DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
|
|
|
- break;
|
|
|
- }
|
|
|
}
|
|
|
|
|
|
-static struct exynos_drm_display_ops hdmi_display_ops = {
|
|
|
- .create_connector = hdmi_create_connector,
|
|
|
+static struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = {
|
|
|
.mode_fixup = hdmi_mode_fixup,
|
|
|
.mode_set = hdmi_mode_set,
|
|
|
- .dpms = hdmi_dpms,
|
|
|
- .commit = hdmi_commit,
|
|
|
+ .enable = hdmi_enable,
|
|
|
+ .disable = hdmi_disable,
|
|
|
+};
|
|
|
+
|
|
|
+static struct drm_encoder_funcs exynos_hdmi_encoder_funcs = {
|
|
|
+ .destroy = drm_encoder_cleanup,
|
|
|
};
|
|
|
|
|
|
static void hdmi_hotplug_work_func(struct work_struct *work)
|
|
@@ -2157,10 +1809,6 @@ static void hdmi_hotplug_work_func(struct work_struct *work)
|
|
|
|
|
|
hdata = container_of(work, struct hdmi_context, hotplug_work.work);
|
|
|
|
|
|
- mutex_lock(&hdata->hdmi_mutex);
|
|
|
- hdata->hpd = gpio_get_value(hdata->hpd_gpio);
|
|
|
- mutex_unlock(&hdata->hdmi_mutex);
|
|
|
-
|
|
|
if (hdata->drm_dev)
|
|
|
drm_helper_hpd_irq_event(hdata->drm_dev);
|
|
|
}
|
|
@@ -2259,30 +1907,6 @@ fail:
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
-static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata
|
|
|
- (struct device *dev)
|
|
|
-{
|
|
|
- struct device_node *np = dev->of_node;
|
|
|
- struct s5p_hdmi_platform_data *pd;
|
|
|
- u32 value;
|
|
|
-
|
|
|
- pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
|
|
|
- if (!pd)
|
|
|
- goto err_data;
|
|
|
-
|
|
|
- if (!of_find_property(np, "hpd-gpio", &value)) {
|
|
|
- DRM_ERROR("no hpd gpio property found\n");
|
|
|
- goto err_data;
|
|
|
- }
|
|
|
-
|
|
|
- pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0);
|
|
|
-
|
|
|
- return pd;
|
|
|
-
|
|
|
-err_data:
|
|
|
- return NULL;
|
|
|
-}
|
|
|
-
|
|
|
static struct of_device_id hdmi_match_types[] = {
|
|
|
{
|
|
|
.compatible = "samsung,exynos5-hdmi",
|
|
@@ -2306,10 +1930,33 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data)
|
|
|
{
|
|
|
struct drm_device *drm_dev = data;
|
|
|
struct hdmi_context *hdata = dev_get_drvdata(dev);
|
|
|
+ struct drm_encoder *encoder = &hdata->encoder;
|
|
|
+ int ret, pipe;
|
|
|
|
|
|
hdata->drm_dev = drm_dev;
|
|
|
|
|
|
- return exynos_drm_create_enc_conn(drm_dev, &hdata->display);
|
|
|
+ pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
|
|
|
+ EXYNOS_DISPLAY_TYPE_HDMI);
|
|
|
+ if (pipe < 0)
|
|
|
+ return pipe;
|
|
|
+
|
|
|
+ encoder->possible_crtcs = 1 << pipe;
|
|
|
+
|
|
|
+ DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
|
|
|
+
|
|
|
+ drm_encoder_init(drm_dev, encoder, &exynos_hdmi_encoder_funcs,
|
|
|
+ DRM_MODE_ENCODER_TMDS);
|
|
|
+
|
|
|
+ drm_encoder_helper_add(encoder, &exynos_hdmi_encoder_helper_funcs);
|
|
|
+
|
|
|
+ ret = hdmi_create_connector(encoder);
|
|
|
+ if (ret) {
|
|
|
+ DRM_ERROR("failed to create connector ret = %d\n", ret);
|
|
|
+ drm_encoder_cleanup(encoder);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
static void hdmi_unbind(struct device *dev, struct device *master, void *data)
|
|
@@ -2343,43 +1990,30 @@ static struct device_node *hdmi_legacy_phy_dt_binding(struct device *dev)
|
|
|
static int hdmi_probe(struct platform_device *pdev)
|
|
|
{
|
|
|
struct device_node *ddc_node, *phy_node;
|
|
|
- struct s5p_hdmi_platform_data *pdata;
|
|
|
- struct hdmi_driver_data *drv_data;
|
|
|
const struct of_device_id *match;
|
|
|
struct device *dev = &pdev->dev;
|
|
|
struct hdmi_context *hdata;
|
|
|
struct resource *res;
|
|
|
int ret;
|
|
|
|
|
|
- if (!dev->of_node)
|
|
|
- return -ENODEV;
|
|
|
-
|
|
|
- pdata = drm_hdmi_dt_parse_pdata(dev);
|
|
|
- if (!pdata)
|
|
|
- return -EINVAL;
|
|
|
-
|
|
|
hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
|
|
|
if (!hdata)
|
|
|
return -ENOMEM;
|
|
|
|
|
|
- hdata->display.type = EXYNOS_DISPLAY_TYPE_HDMI;
|
|
|
- hdata->display.ops = &hdmi_display_ops;
|
|
|
-
|
|
|
- mutex_init(&hdata->hdmi_mutex);
|
|
|
-
|
|
|
- platform_set_drvdata(pdev, hdata);
|
|
|
-
|
|
|
- match = of_match_node(hdmi_match_types, dev->of_node);
|
|
|
+ match = of_match_device(hdmi_match_types, dev);
|
|
|
if (!match)
|
|
|
return -ENODEV;
|
|
|
|
|
|
- drv_data = (struct hdmi_driver_data *)match->data;
|
|
|
- hdata->type = drv_data->type;
|
|
|
- hdata->phy_confs = drv_data->phy_confs;
|
|
|
- hdata->phy_conf_count = drv_data->phy_conf_count;
|
|
|
+ hdata->drv_data = match->data;
|
|
|
+
|
|
|
+ platform_set_drvdata(pdev, hdata);
|
|
|
|
|
|
- hdata->hpd_gpio = pdata->hpd_gpio;
|
|
|
hdata->dev = dev;
|
|
|
+ hdata->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpio", 0);
|
|
|
+ if (hdata->hpd_gpio < 0) {
|
|
|
+ DRM_ERROR("cannot get hpd gpio property\n");
|
|
|
+ return hdata->hpd_gpio;
|
|
|
+ }
|
|
|
|
|
|
ret = hdmi_resources_init(hdata);
|
|
|
if (ret) {
|
|
@@ -2431,7 +2065,7 @@ out_get_ddc_adpt:
|
|
|
}
|
|
|
|
|
|
out_get_phy_port:
|
|
|
- if (drv_data->is_apb_phy) {
|
|
|
+ if (hdata->drv_data->is_apb_phy) {
|
|
|
hdata->regs_hdmiphy = of_iomap(phy_node, 0);
|
|
|
if (!hdata->regs_hdmiphy) {
|
|
|
DRM_ERROR("failed to ioremap hdmi phy\n");
|
|
@@ -2454,8 +2088,6 @@ out_get_phy_port:
|
|
|
goto err_hdmiphy;
|
|
|
}
|
|
|
|
|
|
- hdata->hpd = gpio_get_value(hdata->hpd_gpio);
|
|
|
-
|
|
|
INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
|
|
|
|
|
|
ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
|