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@@ -26,17 +26,17 @@ static struct clk_onecell_data clk_data;
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#define ASS_CLK_DIV 0x4
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#define ASS_CLK_GATE 0x8
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+/* list of all parent clock list */
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+static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
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+static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
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+
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+#ifdef CONFIG_PM_SLEEP
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static unsigned long reg_save[][2] = {
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{ASS_CLK_SRC, 0},
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{ASS_CLK_DIV, 0},
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{ASS_CLK_GATE, 0},
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};
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-/* list of all parent clock list */
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-static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
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-static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
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-
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-#ifdef CONFIG_PM_SLEEP
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static int exynos_audss_clk_suspend(void)
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{
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int i;
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