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@@ -51,7 +51,7 @@ static unsigned int get_mxclk_freq(void)
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*
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* Input: Frequency to be set.
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*/
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-static void setChipClock(unsigned int frequency)
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+static void set_chip_clock(unsigned int frequency)
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{
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struct pll_value pll;
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unsigned int ulActualMxClk;
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@@ -68,19 +68,19 @@ static void setChipClock(unsigned int frequency)
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pll.clockType = MXCLK_PLL;
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/*
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- * Call calcPllValue() to fill the other fields of PLL structure.
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+ * Call calc_pll_value() to fill the other fields of PLL structure.
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* Sometime, the chip cannot set up the exact clock
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* required by the User.
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- * Return value of calcPllValue gives the actual possible clock.
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+ * Return value of calc_pll_value gives the actual possible clock.
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*/
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- ulActualMxClk = calcPllValue(frequency, &pll);
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+ ulActualMxClk = calc_pll_value(frequency, &pll);
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/* Master Clock Control: MXCLK_PLL */
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- POKE32(MXCLK_PLL_CTRL, formatPllReg(&pll));
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+ POKE32(MXCLK_PLL_CTRL, format_pll_reg(&pll));
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}
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}
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-static void setMemoryClock(unsigned int frequency)
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+static void set_memory_clock(unsigned int frequency)
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{
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unsigned int reg, divisor;
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@@ -119,7 +119,7 @@ static void setMemoryClock(unsigned int frequency)
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break;
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}
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- setCurrentGate(reg);
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+ set_current_gate(reg);
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}
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}
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@@ -131,7 +131,7 @@ static void setMemoryClock(unsigned int frequency)
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* NOTE:
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* The maximum frequency the engine can run is 168MHz.
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*/
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-static void setMasterClock(unsigned int frequency)
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+static void set_master_clock(unsigned int frequency)
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{
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unsigned int reg, divisor;
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@@ -169,11 +169,11 @@ static void setMasterClock(unsigned int frequency)
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break;
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}
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- setCurrentGate(reg);
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+ set_current_gate(reg);
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}
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}
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-unsigned int ddk750_getVMSize(void)
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+unsigned int ddk750_get_vm_size(void)
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{
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unsigned int reg;
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unsigned int data;
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@@ -205,18 +205,18 @@ unsigned int ddk750_getVMSize(void)
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return data;
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}
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-int ddk750_initHw(struct initchip_param *pInitParam)
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+int ddk750_init_hw(struct initchip_param *pInitParam)
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{
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unsigned int reg;
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if (pInitParam->powerMode != 0)
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pInitParam->powerMode = 0;
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- setPowerMode(pInitParam->powerMode);
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+ set_power_mode(pInitParam->powerMode);
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/* Enable display power gate & LOCALMEM power gate*/
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reg = PEEK32(CURRENT_GATE);
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reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM);
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- setCurrentGate(reg);
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+ set_current_gate(reg);
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if (sm750_get_chip_type() != SM750LE) {
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/* set panel pll and graphic mode via mmio_88 */
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@@ -232,13 +232,13 @@ int ddk750_initHw(struct initchip_param *pInitParam)
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}
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/* Set the Main Chip Clock */
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- setChipClock(MHz((unsigned int)pInitParam->chipClock));
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+ set_chip_clock(MHz((unsigned int)pInitParam->chipClock));
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/* Set up memory clock. */
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- setMemoryClock(MHz(pInitParam->memClock));
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+ set_memory_clock(MHz(pInitParam->memClock));
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/* Set up master clock */
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- setMasterClock(MHz(pInitParam->masterClock));
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+ set_master_clock(MHz(pInitParam->masterClock));
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/* Reset the memory controller.
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@@ -304,7 +304,7 @@ int ddk750_initHw(struct initchip_param *pInitParam)
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* M = {1,...,255}
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* N = {2,...,15}
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*/
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-unsigned int calcPllValue(unsigned int request_orig, struct pll_value *pll)
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+unsigned int calc_pll_value(unsigned int request_orig, struct pll_value *pll)
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{
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/* as sm750 register definition,
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* N located in 2,15 and M located in 1,255
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@@ -372,7 +372,7 @@ unsigned int calcPllValue(unsigned int request_orig, struct pll_value *pll)
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return ret;
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}
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-unsigned int formatPllReg(struct pll_value *pPLL)
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+unsigned int format_pll_reg(struct pll_value *pPLL)
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{
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#ifndef VALIDATION_CHIP
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unsigned int POD = pPLL->POD;
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