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@@ -51,16 +51,73 @@ static void __iomem *twd_base;
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#define IRQ_LOCALTIMER 29
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-#ifdef CONFIG_OMAP4_ERRATA_I688
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+#ifdef CONFIG_OMAP_INTERCONNECT_BARRIER
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+
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/* Used to implement memory barrier on DRAM path */
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#define OMAP4_DRAM_BARRIER_VA 0xfe600000
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-void __iomem *dram_sync, *sram_sync;
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+static void __iomem *dram_sync, *sram_sync;
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+static phys_addr_t dram_sync_paddr;
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+static u32 dram_sync_size;
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+
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+/*
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+ * The OMAP4 bus structure contains asynchrnous bridges which can buffer
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+ * data writes from the MPU. These asynchronous bridges can be found on
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+ * paths between the MPU to EMIF, and the MPU to L3 interconnects.
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+ *
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+ * We need to be careful about re-ordering which can happen as a result
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+ * of different accesses being performed via different paths, and
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+ * therefore different asynchronous bridges.
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+ */
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-static phys_addr_t paddr;
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-static u32 size;
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+/*
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+ * OMAP4 interconnect barrier which is called for each mb() and wmb().
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+ * This is to ensure that normal paths to DRAM (normal memory, cacheable
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+ * accesses) are properly synchronised with writes to DMA coherent memory
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+ * (normal memory, uncacheable) and device writes.
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+ *
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+ * The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
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+ * path, as we need to ensure that data is visible to other system
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+ * masters prior to writes to those system masters being seen.
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+ *
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+ * Note: the SRAM path is not synchronised via mb() and wmb().
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+ */
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+static void omap4_mb(void)
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+{
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+ if (dram_sync)
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+ writel_relaxed(0, dram_sync);
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+}
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-void omap_bus_sync(void)
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+/*
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+ * OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI.
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+ *
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+ * If a data is stalled inside asynchronous bridge because of back
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+ * pressure, it may be accepted multiple times, creating pointer
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+ * misalignment that will corrupt next transfers on that data path until
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+ * next reset of the system. No recovery procedure once the issue is hit,
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+ * the path remains consistently broken.
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+ *
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+ * Async bridges can be found on paths between MPU to EMIF and MPU to L3
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+ * interconnects.
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+ *
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+ * This situation can happen only when the idle is initiated by a Master
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+ * Request Disconnection (which is trigged by software when executing WFI
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+ * on the CPU).
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+ *
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+ * The work-around for this errata needs all the initiators connected
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+ * through an async bridge to ensure that data path is properly drained
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+ * before issuing WFI. This condition will be met if one Strongly ordered
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+ * access is performed to the target right before executing the WFI.
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+ *
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+ * In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
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+ * IO barrier ensure that there is no synchronisation loss on initiators
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+ * operating on both interconnect port simultaneously.
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+ *
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+ * This is a stronger version of the OMAP4 memory barrier below, and
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+ * operates on both the MPU->MA->EMIF path but also the MPU->OCP path
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+ * as well, and is necessary prior to executing a WFI.
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+ */
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+void omap_interconnect_sync(void)
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{
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if (dram_sync && sram_sync) {
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writel_relaxed(readl_relaxed(dram_sync), dram_sync);
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@@ -68,7 +125,6 @@ void omap_bus_sync(void)
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isb();
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}
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}
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-EXPORT_SYMBOL(omap_bus_sync);
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static int __init omap4_sram_init(void)
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{
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@@ -79,7 +135,7 @@ static int __init omap4_sram_init(void)
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if (!np)
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pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
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__func__);
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- sram_pool = of_get_named_gen_pool(np, "sram", 0);
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+ sram_pool = of_gen_pool_get(np, "sram", 0);
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if (!sram_pool)
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pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
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__func__);
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@@ -91,13 +147,10 @@ static int __init omap4_sram_init(void)
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omap_arch_initcall(omap4_sram_init);
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/* Steal one page physical memory for barrier implementation */
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-int __init omap_barrier_reserve_memblock(void)
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+void __init omap_barrier_reserve_memblock(void)
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{
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-
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- size = ALIGN(PAGE_SIZE, SZ_1M);
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- paddr = arm_memblock_steal(size, SZ_1M);
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-
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- return 0;
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+ dram_sync_size = ALIGN(PAGE_SIZE, SZ_1M);
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+ dram_sync_paddr = arm_memblock_steal(dram_sync_size, SZ_1M);
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}
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void __init omap_barriers_init(void)
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@@ -105,19 +158,18 @@ void __init omap_barriers_init(void)
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struct map_desc dram_io_desc[1];
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dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
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- dram_io_desc[0].pfn = __phys_to_pfn(paddr);
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- dram_io_desc[0].length = size;
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+ dram_io_desc[0].pfn = __phys_to_pfn(dram_sync_paddr);
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+ dram_io_desc[0].length = dram_sync_size;
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dram_io_desc[0].type = MT_MEMORY_RW_SO;
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iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
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dram_sync = (void __iomem *) dram_io_desc[0].virtual;
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- pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
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- (long long) paddr, dram_io_desc[0].virtual);
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+ pr_info("OMAP4: Map %pa to %p for dram barrier\n",
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+ &dram_sync_paddr, dram_sync);
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+ soc_mb = omap4_mb;
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}
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-#else
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-void __init omap_barriers_init(void)
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-{}
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+
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#endif
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void gic_dist_disable(void)
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Russell King