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@@ -4,6 +4,21 @@
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menu "Bus devices"
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+config ARM_CCI
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+ bool "ARM CCI driver support"
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+ depends on ARM && OF && CPU_V7
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+ help
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+ Driver supporting the CCI cache coherent interconnect for ARM
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+ platforms.
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+
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+config ARM_CCN
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+ bool "ARM CCN driver support"
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+ depends on ARM || ARM64
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+ depends on PERF_EVENTS
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+ help
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+ PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
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+ interconnect.
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+
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config BRCMSTB_GISB_ARB
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bool "Broadcom STB GISB bus arbiter"
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depends on ARM || MIPS
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@@ -27,15 +42,6 @@ config MVEBU_MBUS
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Driver needed for the MBus configuration on Marvell EBU SoCs
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(Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
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-config OMAP_OCP2SCP
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- tristate "OMAP OCP2SCP DRIVER"
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- depends on ARCH_OMAP2PLUS
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- help
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- Driver to enable ocp2scp module which transforms ocp interface
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- protocol to scp protocol. In OMAP4, USB PHY is connected via
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- OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
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- OCP2SCP.
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-
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config OMAP_INTERCONNECT
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tristate "OMAP INTERCONNECT DRIVER"
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depends on ARCH_OMAP2PLUS
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@@ -43,20 +49,27 @@ config OMAP_INTERCONNECT
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help
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Driver to enable OMAP interconnect error handling driver.
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-config ARM_CCI
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- bool "ARM CCI driver support"
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- depends on ARM && OF && CPU_V7
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+config OMAP_OCP2SCP
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+ tristate "OMAP OCP2SCP DRIVER"
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+ depends on ARCH_OMAP2PLUS
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help
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- Driver supporting the CCI cache coherent interconnect for ARM
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- platforms.
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+ Driver to enable ocp2scp module which transforms ocp interface
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+ protocol to scp protocol. In OMAP4, USB PHY is connected via
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+ OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
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+ OCP2SCP.
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-config ARM_CCN
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- bool "ARM CCN driver support"
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- depends on ARM || ARM64
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- depends on PERF_EVENTS
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+config SIMPLE_PM_BUS
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+ bool "Simple Power-Managed Bus Driver"
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+ depends on OF && PM
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+ depends on ARCH_SHMOBILE || COMPILE_TEST
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help
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- PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
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- interconnect.
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+ Driver for transparent busses that don't need a real driver, but
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+ where the bus controller is part of a PM domain, or under the control
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+ of a functional clock, and thus relies on runtime PM for managing
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+ this PM domain and/or clock.
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+ An example of such a bus controller is the Renesas Bus State
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+ Controller (BSC, sometimes called "LBSC within Bus Bridge", or
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+ "External Bus Interface") as found on several Renesas ARM SoCs.
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config VEXPRESS_CONFIG
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bool "Versatile Express configuration bus"
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