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@@ -100,6 +100,14 @@
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/* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */
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#define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32) adr)) % ALIGNMENT)
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+#ifdef __BIG_ENDIAN
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+#define xemaclite_readl ioread32be
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+#define xemaclite_writel iowrite32be
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+#else
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+#define xemaclite_readl ioread32
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+#define xemaclite_writel iowrite32
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+#endif
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+
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/**
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* struct net_local - Our private per device data
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* @ndev: instance of the network device
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@@ -156,15 +164,15 @@ static void xemaclite_enable_interrupts(struct net_local *drvdata)
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u32 reg_data;
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/* Enable the Tx interrupts for the first Buffer */
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- reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);
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- __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
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- drvdata->base_addr + XEL_TSR_OFFSET);
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+ reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
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+ xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
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+ drvdata->base_addr + XEL_TSR_OFFSET);
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/* Enable the Rx interrupts for the first buffer */
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- __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
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+ xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
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/* Enable the Global Interrupt Enable */
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- __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
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+ xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
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}
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/**
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@@ -179,17 +187,17 @@ static void xemaclite_disable_interrupts(struct net_local *drvdata)
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u32 reg_data;
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/* Disable the Global Interrupt Enable */
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- __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
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+ xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
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/* Disable the Tx interrupts for the first buffer */
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- reg_data = __raw_readl(drvdata->base_addr + XEL_TSR_OFFSET);
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- __raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),
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- drvdata->base_addr + XEL_TSR_OFFSET);
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+ reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
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+ xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),
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+ drvdata->base_addr + XEL_TSR_OFFSET);
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/* Disable the Rx interrupts for the first buffer */
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- reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET);
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- __raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),
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- drvdata->base_addr + XEL_RSR_OFFSET);
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+ reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET);
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+ xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),
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+ drvdata->base_addr + XEL_RSR_OFFSET);
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}
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/**
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@@ -321,7 +329,7 @@ static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
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byte_count = ETH_FRAME_LEN;
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/* Check if the expected buffer is available */
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- reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
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+ reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
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if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
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XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
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@@ -334,7 +342,7 @@ static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
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addr = (void __iomem __force *)((u32 __force)addr ^
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XEL_BUFFER_OFFSET);
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- reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
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+ reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
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if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
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XEL_TSR_XMIT_ACTIVE_MASK)) != 0)
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@@ -345,16 +353,16 @@ static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
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/* Write the frame to the buffer */
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xemaclite_aligned_write(data, (u32 __force *) addr, byte_count);
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- __raw_writel((byte_count & XEL_TPLR_LENGTH_MASK),
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- addr + XEL_TPLR_OFFSET);
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+ xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK),
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+ addr + XEL_TPLR_OFFSET);
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/* Update the Tx Status Register to indicate that there is a
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* frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which
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* is used by the interrupt handler to check whether a frame
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* has been transmitted */
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- reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
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+ reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
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reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK);
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- __raw_writel(reg_data, addr + XEL_TSR_OFFSET);
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+ xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET);
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return 0;
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}
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@@ -369,7 +377,7 @@ static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
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*
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* Return: Total number of bytes received
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*/
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-static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data)
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+static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen)
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{
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void __iomem *addr;
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u16 length, proto_type;
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@@ -379,7 +387,7 @@ static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data)
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addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);
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/* Verify which buffer has valid data */
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- reg_data = __raw_readl(addr + XEL_RSR_OFFSET);
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+ reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
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if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
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if (drvdata->rx_ping_pong != 0)
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@@ -396,27 +404,28 @@ static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data)
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return 0; /* No data was available */
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/* Verify that buffer has valid data */
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- reg_data = __raw_readl(addr + XEL_RSR_OFFSET);
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+ reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
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if ((reg_data & XEL_RSR_RECV_DONE_MASK) !=
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XEL_RSR_RECV_DONE_MASK)
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return 0; /* No data was available */
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}
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/* Get the protocol type of the ethernet frame that arrived */
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- proto_type = ((ntohl(__raw_readl(addr + XEL_HEADER_OFFSET +
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+ proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET +
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XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) &
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XEL_RPLR_LENGTH_MASK);
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/* Check if received ethernet frame is a raw ethernet frame
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* or an IP packet or an ARP packet */
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- if (proto_type > (ETH_FRAME_LEN + ETH_FCS_LEN)) {
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+ if (proto_type > ETH_DATA_LEN) {
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if (proto_type == ETH_P_IP) {
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- length = ((ntohl(__raw_readl(addr +
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+ length = ((ntohl(xemaclite_readl(addr +
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XEL_HEADER_IP_LENGTH_OFFSET +
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XEL_RXBUFF_OFFSET)) >>
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XEL_HEADER_SHIFT) &
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XEL_RPLR_LENGTH_MASK);
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+ length = min_t(u16, length, ETH_DATA_LEN);
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length += ETH_HLEN + ETH_FCS_LEN;
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} else if (proto_type == ETH_P_ARP)
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@@ -429,14 +438,17 @@ static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data)
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/* Use the length in the frame, plus the header and trailer */
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length = proto_type + ETH_HLEN + ETH_FCS_LEN;
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+ if (WARN_ON(length > maxlen))
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+ length = maxlen;
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+
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/* Read from the EmacLite device */
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xemaclite_aligned_read((u32 __force *) (addr + XEL_RXBUFF_OFFSET),
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data, length);
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/* Acknowledge the frame */
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- reg_data = __raw_readl(addr + XEL_RSR_OFFSET);
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+ reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
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reg_data &= ~XEL_RSR_RECV_DONE_MASK;
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- __raw_writel(reg_data, addr + XEL_RSR_OFFSET);
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+ xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET);
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return length;
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}
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@@ -463,14 +475,14 @@ static void xemaclite_update_address(struct net_local *drvdata,
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xemaclite_aligned_write(address_ptr, (u32 __force *) addr, ETH_ALEN);
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- __raw_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET);
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+ xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET);
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/* Update the MAC address in the EmacLite */
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- reg_data = __raw_readl(addr + XEL_TSR_OFFSET);
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- __raw_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET);
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+ reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
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+ xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET);
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/* Wait for EmacLite to finish with the MAC address update */
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- while ((__raw_readl(addr + XEL_TSR_OFFSET) &
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+ while ((xemaclite_readl(addr + XEL_TSR_OFFSET) &
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XEL_TSR_PROG_MAC_ADDR) != 0)
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;
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}
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@@ -603,7 +615,7 @@ static void xemaclite_rx_handler(struct net_device *dev)
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skb_reserve(skb, 2);
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- len = xemaclite_recv_data(lp, (u8 *) skb->data);
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+ len = xemaclite_recv_data(lp, (u8 *) skb->data, len);
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if (!len) {
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dev->stats.rx_errors++;
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@@ -640,32 +652,32 @@ static irqreturn_t xemaclite_interrupt(int irq, void *dev_id)
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u32 tx_status;
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/* Check if there is Rx Data available */
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- if ((__raw_readl(base_addr + XEL_RSR_OFFSET) &
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+ if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) &
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XEL_RSR_RECV_DONE_MASK) ||
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- (__raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
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+ (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
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& XEL_RSR_RECV_DONE_MASK))
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xemaclite_rx_handler(dev);
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/* Check if the Transmission for the first buffer is completed */
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- tx_status = __raw_readl(base_addr + XEL_TSR_OFFSET);
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+ tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET);
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if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
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(tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
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tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
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- __raw_writel(tx_status, base_addr + XEL_TSR_OFFSET);
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+ xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET);
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tx_complete = true;
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}
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/* Check if the Transmission for the second buffer is completed */
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- tx_status = __raw_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
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+ tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
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if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
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(tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
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tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
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- __raw_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +
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- XEL_TSR_OFFSET);
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+ xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +
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+ XEL_TSR_OFFSET);
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tx_complete = true;
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}
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@@ -698,7 +710,7 @@ static int xemaclite_mdio_wait(struct net_local *lp)
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/* wait for the MDIO interface to not be busy or timeout
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after some time.
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*/
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- while (__raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) &
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+ while (xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) &
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XEL_MDIOCTRL_MDIOSTS_MASK) {
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if (time_before_eq(end, jiffies)) {
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WARN_ON(1);
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@@ -734,17 +746,17 @@ static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg)
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* MDIO Address register. Set the Status bit in the MDIO Control
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* register to start a MDIO read transaction.
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*/
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- ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
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- __raw_writel(XEL_MDIOADDR_OP_MASK |
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- ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
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- lp->base_addr + XEL_MDIOADDR_OFFSET);
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- __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
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- lp->base_addr + XEL_MDIOCTRL_OFFSET);
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+ ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
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+ xemaclite_writel(XEL_MDIOADDR_OP_MASK |
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+ ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
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+ lp->base_addr + XEL_MDIOADDR_OFFSET);
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+ xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
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+ lp->base_addr + XEL_MDIOCTRL_OFFSET);
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if (xemaclite_mdio_wait(lp))
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return -ETIMEDOUT;
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- rc = __raw_readl(lp->base_addr + XEL_MDIORD_OFFSET);
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+ rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET);
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dev_dbg(&lp->ndev->dev,
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"xemaclite_mdio_read(phy_id=%i, reg=%x) == %x\n",
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@@ -781,13 +793,13 @@ static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg,
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* Data register. Finally, set the Status bit in the MDIO Control
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* register to start a MDIO write transaction.
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*/
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- ctrl_reg = __raw_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
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- __raw_writel(~XEL_MDIOADDR_OP_MASK &
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- ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
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- lp->base_addr + XEL_MDIOADDR_OFFSET);
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- __raw_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);
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- __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
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- lp->base_addr + XEL_MDIOCTRL_OFFSET);
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+ ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
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+ xemaclite_writel(~XEL_MDIOADDR_OP_MASK &
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+ ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
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+ lp->base_addr + XEL_MDIOADDR_OFFSET);
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+ xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);
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+ xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
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+ lp->base_addr + XEL_MDIOCTRL_OFFSET);
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return 0;
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}
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@@ -834,8 +846,8 @@ static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev)
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/* Enable the MDIO bus by asserting the enable bit in MDIO Control
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* register.
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*/
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- __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK,
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- lp->base_addr + XEL_MDIOCTRL_OFFSET);
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+ xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK,
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+ lp->base_addr + XEL_MDIOCTRL_OFFSET);
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bus = mdiobus_alloc();
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if (!bus) {
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@@ -1126,8 +1138,8 @@ static int xemaclite_of_probe(struct platform_device *ofdev)
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}
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/* Clear the Tx CSR's in case this is a restart */
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- __raw_writel(0, lp->base_addr + XEL_TSR_OFFSET);
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- __raw_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
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+ xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET);
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+ xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
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/* Set the MAC address in the EmacLite device */
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xemaclite_update_address(lp, ndev->dev_addr);
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