|
@@ -3290,6 +3290,19 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
|
|
|
|
+ uint32_t reg, uint32_t val)
|
|
|
|
+{
|
|
|
|
+ int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
|
|
|
|
+
|
|
|
|
+ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
|
|
|
|
+ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
|
|
|
|
+ WRITE_DATA_DST_SEL(0)));
|
|
|
|
+ amdgpu_ring_write(ring, reg);
|
|
|
|
+ amdgpu_ring_write(ring, 0);
|
|
|
|
+ amdgpu_ring_write(ring, val);
|
|
|
|
+}
|
|
|
|
+
|
|
/*
|
|
/*
|
|
* RLC
|
|
* RLC
|
|
* The RLC is a multi-purpose microengine that handles a
|
|
* The RLC is a multi-purpose microengine that handles a
|
|
@@ -5134,6 +5147,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
|
|
.insert_nop = amdgpu_ring_insert_nop,
|
|
.insert_nop = amdgpu_ring_insert_nop,
|
|
.pad_ib = amdgpu_ring_generic_pad_ib,
|
|
.pad_ib = amdgpu_ring_generic_pad_ib,
|
|
.emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
|
|
.emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
|
|
|
|
+ .emit_wreg = gfx_v7_0_ring_emit_wreg,
|
|
};
|
|
};
|
|
|
|
|
|
static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
|
|
static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
|
|
@@ -5163,6 +5177,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
|
|
.test_ib = gfx_v7_0_ring_test_ib,
|
|
.test_ib = gfx_v7_0_ring_test_ib,
|
|
.insert_nop = amdgpu_ring_insert_nop,
|
|
.insert_nop = amdgpu_ring_insert_nop,
|
|
.pad_ib = amdgpu_ring_generic_pad_ib,
|
|
.pad_ib = amdgpu_ring_generic_pad_ib,
|
|
|
|
+ .emit_wreg = gfx_v7_0_ring_emit_wreg,
|
|
};
|
|
};
|
|
|
|
|
|
static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
|
|
static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
|