soc: rockchip: power-domain: Don't (incorrectly) set rk3399 up/down counts

On rk3288 it was important that powerdown and powerup counts for the
CPU/GPU in the kernel because:
* The power on default was crazy long.
* We couldn't rely on the firmware to set this up because really this
  wasn't the firmware's job--the kernel was the only one that really
  cared about bringing up / down CPUs and the GPU and doing suspend /
  resume (which involves bringing up / down CPUs).

On newer ARM systems (like rk3399) ARM Trusted Firmware is in charge of
bringing up and down the CPUs and it really should be in charge of
setting all these counts right.  After all ATF is in charge of suspend /
resume and CPU up / down.  Let's get out of the way and let ATF do its
job.

A few other motivations for doing this:
* Depending on another configuration (PMU_24M_EN_CFG) these counts can
  be either in 24M or 32k cycles.  Thus, though ATF isn't really so
  involved in bringing up the GPU, ATF should probably manage the counts
  for everything so it can also manage the 24M / 32k choice.
* It turns out that (right now) 24M mode is broken on rk3399 and not
  being used.  That means that the count the kernel was programming
  in (24) was not 1 us (which it seems was intended) but was actually
  .75 ms
* On rk3399 there are actually 2 separate registers for setting CPU
  up/down time plus 1 register for GPU up/down time.  The curent kernel
  code actually was putting the register for the "little" cores in the
  "CPU" slot and the register for the "big" cores in the "GPU" slot.  It
  was never initting the GPU counts.

Note: this change assumes that ATF will actually set these values at
boot, as I'm proposing in <http://crosreview.com/372381>.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
[ATF change has landed]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

drivers/soc/rockchip/pm_domains.c

@@ -597,10 +597,12 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev)
 	 * Configure power up and down transition delays for CORE
 	 * and GPU domains.
 	 */
-	rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
-				  pmu_info->core_power_transition_time);
-	rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
-				  pmu_info->gpu_power_transition_time);
+	if (pmu_info->core_power_transition_time)
+		rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
+					pmu_info->core_power_transition_time);
+	if (pmu_info->gpu_pwrcnt_offset)
+		rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
+					pmu_info->gpu_power_transition_time);
 
 	error = -ENODEV;
 
@@ -722,11 +724,7 @@ static const struct rockchip_pmu_info rk3399_pmu = {
 	.idle_offset = 0x64,
 	.ack_offset = 0x68,
 
-	.core_pwrcnt_offset = 0x9c,
-	.gpu_pwrcnt_offset = 0xa4,
-
-	.core_power_transition_time = 24,
-	.gpu_power_transition_time = 24,
+	/* ARM Trusted Firmware manages power transition times */
 
 	.num_domains = ARRAY_SIZE(rk3399_pm_domains),
 	.domain_info = rk3399_pm_domains,