|
@@ -1701,7 +1701,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
|
|
struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
|
|
struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
|
|
u32 linetime, ips_linetime;
|
|
u32 linetime, ips_linetime;
|
|
|
|
|
|
- if (!intel_crtc_active(crtc))
|
|
|
|
|
|
+ if (!intel_crtc->active)
|
|
return 0;
|
|
return 0;
|
|
|
|
|
|
/* The WM are computed with base on how long it takes to fill a single
|
|
/* The WM are computed with base on how long it takes to fill a single
|
|
@@ -1956,7 +1956,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
struct drm_plane *plane;
|
|
struct drm_plane *plane;
|
|
|
|
|
|
- if (!intel_crtc_active(crtc))
|
|
|
|
|
|
+ if (!intel_crtc->active)
|
|
return;
|
|
return;
|
|
|
|
|
|
p->active = true;
|
|
p->active = true;
|
|
@@ -2468,7 +2468,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
|
|
|
|
|
|
nth_active_pipe = 0;
|
|
nth_active_pipe = 0;
|
|
for_each_crtc(dev, crtc) {
|
|
for_each_crtc(dev, crtc) {
|
|
- if (!intel_crtc_active(crtc))
|
|
|
|
|
|
+ if (!to_intel_crtc(crtc)->active)
|
|
continue;
|
|
continue;
|
|
|
|
|
|
if (crtc == for_crtc)
|
|
if (crtc == for_crtc)
|
|
@@ -2708,7 +2708,7 @@ static void skl_compute_wm_global_parameters(struct drm_device *dev,
|
|
struct drm_plane *plane;
|
|
struct drm_plane *plane;
|
|
|
|
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
|
|
- config->num_pipes_active += intel_crtc_active(crtc);
|
|
|
|
|
|
+ config->num_pipes_active += to_intel_crtc(crtc)->active;
|
|
|
|
|
|
/* FIXME: I don't think we need those two global parameters on SKL */
|
|
/* FIXME: I don't think we need those two global parameters on SKL */
|
|
list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
|
|
list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
|
|
@@ -2729,7 +2729,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb;
|
|
struct drm_framebuffer *fb;
|
|
int i = 1; /* Index for sprite planes start */
|
|
int i = 1; /* Index for sprite planes start */
|
|
|
|
|
|
- p->active = intel_crtc_active(crtc);
|
|
|
|
|
|
+ p->active = intel_crtc->active;
|
|
if (p->active) {
|
|
if (p->active) {
|
|
p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
|
|
p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
|
|
p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
|
|
p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
|
|
@@ -2860,7 +2860,7 @@ static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
|
|
static uint32_t
|
|
static uint32_t
|
|
skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
|
|
skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
|
|
{
|
|
{
|
|
- if (!intel_crtc_active(crtc))
|
|
|
|
|
|
+ if (!to_intel_crtc(crtc)->active)
|
|
return 0;
|
|
return 0;
|
|
|
|
|
|
return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
|
|
return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
|
|
@@ -3407,7 +3407,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
|
|
hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
|
|
hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
|
|
hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
|
|
hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
|
|
|
|
|
|
- if (!intel_crtc_active(crtc))
|
|
|
|
|
|
+ if (!intel_crtc->active)
|
|
return;
|
|
return;
|
|
|
|
|
|
hw->dirty[pipe] = true;
|
|
hw->dirty[pipe] = true;
|
|
@@ -3462,7 +3462,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
|
|
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
|
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
|
hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
|
|
hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
|
|
|
|
|
|
- active->pipe_enabled = intel_crtc_active(crtc);
|
|
|
|
|
|
+ active->pipe_enabled = intel_crtc->active;
|
|
|
|
|
|
if (active->pipe_enabled) {
|
|
if (active->pipe_enabled) {
|
|
u32 tmp = hw->wm_pipe[pipe];
|
|
u32 tmp = hw->wm_pipe[pipe];
|