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@@ -374,7 +374,7 @@ int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
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}
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EXPORT_SYMBOL_GPL(ni_tio_arm);
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-static unsigned ni_660x_source_select_bits(unsigned int clock_source)
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+static unsigned ni_660x_clk_src(unsigned int clock_source)
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{
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unsigned clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
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unsigned ni_660x_clock;
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@@ -426,7 +426,7 @@ static unsigned ni_660x_source_select_bits(unsigned int clock_source)
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return Gi_Source_Select_Bits(ni_660x_clock);
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}
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-static unsigned ni_m_series_source_select_bits(unsigned int clock_source)
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+static unsigned ni_m_clk_src(unsigned int clock_source)
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{
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unsigned clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
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unsigned ni_m_series_clock;
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@@ -520,52 +520,44 @@ static int ni_tio_set_clock_src(struct ni_gpct *counter,
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{
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struct ni_gpct_device *counter_dev = counter->counter_dev;
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unsigned cidx = counter->counter_index;
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- unsigned input_select_bits = 0;
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- static const uint64_t pico_per_nano = 1000;
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+ unsigned bits = 0;
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-/*FIXME: validate clock source */
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+ /* FIXME: validate clock source */
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switch (counter_dev->variant) {
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case ni_gpct_variant_660x:
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- input_select_bits |= ni_660x_source_select_bits(clock_source);
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+ bits |= ni_660x_clk_src(clock_source);
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break;
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case ni_gpct_variant_e_series:
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case ni_gpct_variant_m_series:
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default:
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- input_select_bits |=
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- ni_m_series_source_select_bits(clock_source);
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+ bits |= ni_m_clk_src(clock_source);
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break;
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}
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if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
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- input_select_bits |= Gi_Source_Polarity_Bit;
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+ bits |= Gi_Source_Polarity_Bit;
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ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
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- Gi_Source_Select_Mask | Gi_Source_Polarity_Bit,
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- input_select_bits);
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+ Gi_Source_Select_Mask | Gi_Source_Polarity_Bit, bits);
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ni_tio_set_source_subselect(counter, clock_source);
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- if (ni_tio_counting_mode_registers_present(counter_dev)) {
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- const unsigned prescaling_mode =
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- clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK;
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- unsigned counting_mode_bits = 0;
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- switch (prescaling_mode) {
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+ if (ni_tio_counting_mode_registers_present(counter_dev)) {
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+ bits = 0;
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+ switch (clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
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case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
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break;
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case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
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- counting_mode_bits |=
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- Gi_Prescale_X2_Bit(counter_dev->variant);
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+ bits |= Gi_Prescale_X2_Bit(counter_dev->variant);
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break;
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case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
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- counting_mode_bits |=
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- Gi_Prescale_X8_Bit(counter_dev->variant);
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+ bits |= Gi_Prescale_X8_Bit(counter_dev->variant);
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break;
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default:
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return -EINVAL;
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}
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ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
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Gi_Prescale_X2_Bit(counter_dev->variant) |
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- Gi_Prescale_X8_Bit(counter_dev->variant),
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- counting_mode_bits);
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+ Gi_Prescale_X8_Bit(counter_dev->variant), bits);
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}
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- counter->clock_period_ps = pico_per_nano * period_ns;
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+ counter->clock_period_ps = period_ns * 1000;
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ni_tio_set_sync_mode(counter, 0);
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return 0;
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}
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