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@@ -33,12 +33,15 @@ static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,
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static int register_process_cik(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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static int initialize_cpsch_cik(struct device_queue_manager *dqm);
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+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
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+ struct qcm_process_device *qpd);
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void device_queue_manager_init_cik(struct device_queue_manager_asic_ops *ops)
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{
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ops->set_cache_memory_policy = set_cache_memory_policy_cik;
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ops->register_process = register_process_cik;
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ops->initialize = initialize_cpsch_cik;
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+ ops->init_sdma_vm = init_sdma_vm;
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}
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static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
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@@ -129,6 +132,19 @@ static int register_process_cik(struct device_queue_manager *dqm,
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return 0;
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}
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+static void init_sdma_vm(struct device_queue_manager *dqm, struct queue *q,
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+ struct qcm_process_device *qpd)
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+{
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+ uint32_t value = SDMA_ATC;
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+
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+ if (q->process->is_32bit_user_mode)
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+ value |= SDMA_VA_PTR32 | get_sh_mem_bases_32(qpd_to_pdd(qpd));
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+ else
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+ value |= SDMA_VA_SHARED_BASE(get_sh_mem_bases_nybble_64(
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+ qpd_to_pdd(qpd)));
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+ q->properties.sdma_vm_addr = value;
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+}
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+
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static int initialize_cpsch_cik(struct device_queue_manager *dqm)
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{
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return init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm));
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